Patents by Inventor Yoshihisa Dotta

Yoshihisa Dotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040080013
    Abstract: In a chip-stack semiconductor device including multiple semiconductor chips vertically stacked on top of each other, each of the semiconductor chips includes multiple through electrodes connected to each other in regions inside of electrode pads derived from a device region, and each of the through electrodes links a front surface to a back surface of the semiconductor chip. This arrangement provides a chip-stack semiconductor device which can prevent the increase in the size of the device and resolve the difficulty of stacking multiple semiconductor chips on top of each other, both of which are the problems associated with the provision of a number of through electrodes.
    Type: Application
    Filed: September 26, 2003
    Publication date: April 29, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Toshio Kimura, Yoshihisa Dotta
  • Publication number: 20030124769
    Abstract: A semiconductor device includes: a circuit constituting section having (a) a function circuit and (b) an externally-drawing electrode, connected to the function circuit, on a surface of the circuit constituting section; and an insulating layer provided on a side of a rear surface of the circuit constituting section, wherein the insulating layer has a face opposite to the circuit constituting section, and an area of the face is set so as to be larger than an area of the rear surface of the circuit constituting section. Thus, it is possible to clear such problems that an adhesive that has overflowed from a space between the semiconductor device and the circuit substrate adheres to a bonding collet when flip chip bonding is performed.
    Type: Application
    Filed: August 20, 2002
    Publication date: July 3, 2003
    Inventors: Yoshihisa Dotta, Kazuo Tamaki
  • Patent number: 6518090
    Abstract: A semiconductor device includes a circuit board on which a semiconductor chip is mounted via an adhesive resin layer and through which a moisture drain hole is formed. A pit part having a width wider than a diameter of the moisture drain hole is formed in a part of the adhesive resin layer exposed in the moisture drain hole. On this account, the semiconductor device can properly drain moisture to the outside when the semiconductor device is mounted on another packaging substrate by reflowing.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: February 11, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihisa Dotta, Kazuo Tamaki, Yasuyuki Saza
  • Publication number: 20020197771
    Abstract: A semiconductor package includes: a semiconductor chip having circuits formed on a surface, and having a thickness of 0.5 &mgr;m or more and 100 &mgr;m or less; and an adhesive resin layer provided so as to cover the surface of the semiconductor chip on which the circuits are provided.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 26, 2002
    Inventors: Yoshihisa Dotta, Kazuo Tamaki
  • Publication number: 20020076858
    Abstract: A semiconductor device includes a circuit board on which a semiconductor chip is mounted via an adhesive resin layer and through which a moisture drain hole is formed. A pit part having a width wider than a diameter of the moisture drain hole is formed in a part of the adhesive resin layer exposed in the moisture drain hole. On this account, the semiconductor device can properly drain moisture to the outside when the semiconductor device is mounted on another packaging substrate by reflowing.
    Type: Application
    Filed: December 4, 2001
    Publication date: June 20, 2002
    Inventors: Yoshihisa Dotta, Kazuo Tamaki, Yasuyuki Saza
  • Patent number: 6353263
    Abstract: When a first semiconductor chip is installed on a circuit substrate by using an anisotropic conductive bonding agent, one portion thereof is allowed to protrude outside the first semiconductor chip. A second semiconductor chip is installed on the first semiconductor chip and a support portion formed by the protruding resin. The protruding portion of the second semiconductor chip is supported by the support portion from under. Thus, in a semiconductor device having a plurality of laminated semiconductor chips in an attempt to achieve a high density, even when, from a semiconductor chip stacked on a circuit substrate, one portion of a semiconductor chip stacked thereon protrudes, it is possible to carry out a better wire bonding process on electrodes formed on the protruding portion.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: March 5, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihisa Dotta, Yasuyuki Saza, Kazuo Tamaki
  • Patent number: 6157080
    Abstract: A semiconductor device package which eliminates the possibility of damages to a solder connected portion of a flip-chip connected chip by load, or which eliminates ultrasonic output at the time of wire bonding is described. Electrodes of a first chip are connected to first connection pads corresponding to the electrodes with the first chip being bonded at its rear surface to a rear surface of a second chip. A first resin is interposed in a gap between the first chip and a circuit board so as not to cover the first or second connection pads. Thereafter, the electrode of the second chip is connected to the second connection pads by wires, and the whole device is overlayed by a second resin.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: December 5, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuo Tamaki, Yasuyuki Saza, Yoshihisa Dotta
  • Patent number: 5016986
    Abstract: In a liquid crystal display apparatus, in order to reduce the size and weight, an integrated circuit for driving a liquid crystal is mounted on the glass substrate including the liquid crystal panel either directly or by way of a tape carrier. That is, two glass substrates of liquid crystal panel are mutually overlapped with an offset, and a liquid crystal material is injected into the overlapping regions of the two glass substrates, and liquid crystal display is effected in this region. Further, in the non-overlapping region of the two glass substrates, the integrated circuit is connected either directly or by way of a tape carrier. On the glass substrates, electrodes for varying the optical characteristics of the liquid crystals are provided, and the integrated circuit drives the liquid crystal by controlling the voltage applied to the electrodes. Further transparent insulation films are formed usually formed on the electrodes.
    Type: Grant
    Filed: April 12, 1989
    Date of Patent: May 21, 1991
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akihiro Kawashima, Hirokazu Yoshida, Yasunobu Tagusa, Kiyoshi Inada, Hideshi Makita, Yoshihisa Dotta