Patents by Inventor Yoshihisa Fujisaki

Yoshihisa Fujisaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9911916
    Abstract: In order to form a phase change thin film being flat in a nanometer level and having a good coverage, which is essential for realizing a three-dimensional ultra-high integrated phase change memory, an equipment for vapor phase growth of a phase change thin film is provided which form a phase change thin film at low temperature while the film is being kept in a completely amorphous state. A structure is provided in which an ammonia cracker is connected to a reactor of the equipment for vapor phase growth for a nitrogen radical obtained by decomposing ammonia gas. Consequently, low temperature decomposition of metal organic precursor and film formation on a substrate surface are realized. With the use of this equipment, it is possible to realize a completely amorphous film which has a flat surface at a low temperature of 135° C. using an amine complex as a Ge precursor.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 6, 2018
    Assignee: HITACH, LTD.
    Inventors: Yoshihisa Fujisaki, Yoshitaka Sasago, Takashi Kobayashi
  • Publication number: 20170125675
    Abstract: In order to form a phase change thin film being flat in a nanometer level and having a good coverage, which is essential for realizing a three-dimensional ultra-high integrated phase change memory, an equipment for vapor phase growth of a phase change thin film is provided which form a phase change thin film at low temperature while the film is being kept in a completely amorphous state. A structure is provided in which an ammonia cracker is connected to a reactor of the equipment for vapor phase growth for a nitrogen radical obtained by decomposing ammonia gas. Consequently, low temperature decomposition of metal organic precursor and film formation on a substrate surface are realized. With the use of this equipment, it is possible to realize a completely amorphous film which has a flat surface at a low temperature of 135° C. using an amine complex as a Ge precursor.
    Type: Application
    Filed: March 28, 2014
    Publication date: May 4, 2017
    Inventors: Yoshihisa FUJISAKI, Yoshitaka SASAGO, Takashi KOBAYASHI
  • Patent number: 8618523
    Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa
  • Patent number: 8000126
    Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi, Nozomu Matsuzaki, Yoshihisa Fujisaki, Masaharu Kinoshita, Yuichi Matsui
  • Publication number: 20110049454
    Abstract: In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.
    Type: Application
    Filed: June 23, 2006
    Publication date: March 3, 2011
    Inventors: Motoyasu Terao, Yuichi Matsui, Tsuyoshi Koga, Nozomu Matsuzaki, Norikatsu Takaura, Yoshihisa Fujisaki, Kenzo Kurotsuchi, Takahiro Morikawa, Yoshitaka Sasago, Junko Ushiyama, Akemi Hirotsune
  • Patent number: 7864568
    Abstract: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihisa Fujisaki, Satoru Hanzawa, Kenzo Kurotsuchi, Nozomu Matsuzaki, Norikatsu Takaura
  • Patent number: 7859896
    Abstract: A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Kenzo Kurotsuchi, Norikatsu Takaura, Yoshihisa Fujisaki
  • Patent number: 7767997
    Abstract: A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: August 3, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Motoyasu Terao, Norikatsu Takaura, Yoshihisa Fujisaki, Tomoyuki Kodama, Nobuyuki Arasawa
  • Publication number: 20100096613
    Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.
    Type: Application
    Filed: January 11, 2007
    Publication date: April 22, 2010
    Inventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi, Nozomu Matsuzaki, Yoshihisa Fujisaki, Masaharu Kinoshita, Yuichi Matsui
  • Publication number: 20100061132
    Abstract: In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided.
    Type: Application
    Filed: December 7, 2006
    Publication date: March 11, 2010
    Inventors: Yoshihisa Fujisaki, Satoru Hanzawa, Kenzo Kurotsuchi, Nozomu Matsuzaki, Norikatsu Takaura
  • Publication number: 20100012917
    Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
    Type: Application
    Filed: May 31, 2006
    Publication date: January 21, 2010
    Inventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa
  • Publication number: 20090242868
    Abstract: A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably.
    Type: Application
    Filed: February 12, 2009
    Publication date: October 1, 2009
    Inventors: Kenzo KUROTSUCHI, Motoyasu TERAO, Norikatsu TAKAURA, Yoshihisa FUJISAKI, Kazuo ONO, Yoshitaka SASAGO
  • Publication number: 20090052231
    Abstract: A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.
    Type: Application
    Filed: February 2, 2006
    Publication date: February 26, 2009
    Inventors: Kenzo Kurotsuchi, Norikatsu Takaura, Yoshihisa Fujisaki
  • Publication number: 20090039336
    Abstract: The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen.
    Type: Application
    Filed: July 21, 2008
    Publication date: February 12, 2009
    Inventors: Motoyasu Terao, Yoshitaka Sasago, Kenzo Kurotsuchi, Kazuo Ono, Yoshihisa Fujisaki, Norikatsu Takaura, Riichiro Takemura
  • Publication number: 20090014708
    Abstract: A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 15, 2009
    Inventors: Yoshitaka SASAGO, Motoyasu Terao, Norikatsu Takaura, Yoshihisa Fujisaki, Tomoyuki Kodama, Nobuyuki Arasawa
  • Patent number: 7256437
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: August 14, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Patent number: 7033958
    Abstract: A semiconductor apparatus is provided that is thermally stable in a post process and is suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides, and a process is provided for producing the same. In order to achieve a high function formation of a gate insulator, a silicon nitride film having a specific inductive capacity approximately twice as much as that of silicon oxide, and which is thermally stable, is not provided with a Si—H bond and is used as at least a portion of the gate insulator. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having a high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: April 25, 2006
    Assignees: Hitachi, Ltd., Tokyo Institute of Technology.
    Inventors: Yoshihisa Fujisaki, Hiroshi Ishihara
  • Publication number: 20050074936
    Abstract: A method of fabricating a semiconductor device, is provided including forming an insulating film having an opening portion on a substrate having a transistor, filling a conductive film in the opening portion, forming a reaction barrier film functioning to prevent a reaction on the insulating film, and forming a diffusion barrier film on the conductive film. Next a first electrode is formed on the diffusion barrier film, a ferroelectric film, including at least one element of the group consisting of lead, barium and bismuth is formed on the first electrode after the step of forming the reaction barrier film, and a second electrode is formed on the ferroelectric film.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 7, 2005
    Inventors: Kazuyoshi Torii, Hiroshi Miki, Yoshihisa Fujisaki
  • Publication number: 20050051821
    Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
    Type: Application
    Filed: August 18, 2004
    Publication date: March 10, 2005
    Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
  • Patent number: 6822276
    Abstract: It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: November 23, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Torii, Hiroshi Miki, Yoshihisa Fujisaki