Patents by Inventor Yoshihisa Fujisaki
Yoshihisa Fujisaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6818523Abstract: A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.Type: GrantFiled: June 25, 2003Date of Patent: November 16, 2004Assignee: Hitachi, Ltd.Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
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Patent number: 6815741Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.Type: GrantFiled: July 23, 2003Date of Patent: November 9, 2004Assignee: Renesas Technology Corp.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 6800889Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.Type: GrantFiled: February 13, 2002Date of Patent: October 5, 2004Assignee: Hitachi, Ltd.Inventors: Shinichiro Takatani, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Kazuyoshi Torii
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Publication number: 20040124447Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.Type: ApplicationFiled: July 23, 2003Publication date: July 1, 2004Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Publication number: 20040063280Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.Type: ApplicationFiled: June 25, 2003Publication date: April 1, 2004Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
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Publication number: 20040043570Abstract: With regard to a semiconductor apparatus thermally stable in a post process and suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides and a process of producing the same, in order to achieve high function formation of a gate insulator 8, a silicon nitride film specific inductive capacity of which is approximately twice as much as that of silicon oxide and which is thermally stable and is not provided with Si—H bond, is used as at least a portion of the gate insulator 8. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.Type: ApplicationFiled: August 28, 2003Publication date: March 4, 2004Applicants: Hitachi, Ltd., Tokyo Institute of TechnologyInventors: Yoshihisa Fujisaki, Hiroshi Ishihara
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Patent number: 6635913Abstract: The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.Type: GrantFiled: December 27, 2001Date of Patent: October 21, 2003Assignee: Hitachi, Ltd.Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
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Patent number: 6632721Abstract: In a method of manufacturing a semiconductor integrated circuit device in which a lower electrode of a capacitor is composed of a polycrystalline silicon film having a surface area increased by surface roughening, an impurity is introduced into the polycrystalline silicon film by vapor phase diffusion in order to reduce the resistance of the lower electrode.Type: GrantFiled: June 23, 2000Date of Patent: October 14, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Shinpei Iijima, Satoshi Yamamoto, Jun Kuroda, Hiroshi Miki, Yoshihisa Fujisaki, Tadanori Yoshida, Kenichi Yamaguchi
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Patent number: 6630697Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.Type: GrantFiled: July 25, 2001Date of Patent: October 7, 2003Assignee: Hitachi, Ltd.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Publication number: 20020158250Abstract: With regard to a semiconductor apparatus thermally stable in a post process and suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides and a process of producing the same, in order to achieve high function formation of a gate insulator 8, a silicon nitride film specific inductive capacity of which is approximately twice as much as that of silicon oxide and which is thermally stable and is not provided with Si—H bond, is used as at least a portion of the gate insulator 8. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.Type: ApplicationFiled: October 30, 2001Publication date: October 31, 2002Inventors: Yoshihisa Fujisaki, Hiroshi Ishihara
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Patent number: 6462368Abstract: A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.Type: GrantFiled: January 31, 2002Date of Patent: October 8, 2002Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Torii, Yasuhiro Shimamoto, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki
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Publication number: 20020140014Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.Type: ApplicationFiled: February 13, 2002Publication date: October 3, 2002Inventors: Shinichiro Takatani, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Kazuyoshi Torii
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Patent number: 6432767Abstract: A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.Type: GrantFiled: July 3, 2001Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Torii, Hiroshi Kawakami, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Masahiro Moniwa
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Publication number: 20020096701Abstract: A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.Type: ApplicationFiled: January 31, 2002Publication date: July 25, 2002Applicant: Hitachi, Ltd.Inventors: Kazuyoshi Torii, Yasuhiro Shimamoto, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki
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Patent number: 6420192Abstract: A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode delamination. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode, a lower electrode, and a capacitor insulating film (of a high-dielectric-constant or ferroelectric thin film) which is held between electrodes and serves as a capacitor insulating film, and a protective insulating film which covers the capacitor structure and is formed by plasma treatment after electrode formation. An oxygen introducing layer is formed on the surface of the capacitor insulating film. The oxygen introducing layer can be formed on the surface of the high-dielectric-constant or ferroelectric material by introducing oxygen to the boundary between the electrode and the material by conducting heat treatment in an oxygen atmosphere before the protective insulating film (SiO2 passivation film) is formed.Type: GrantFiled: October 3, 2001Date of Patent: July 16, 2002Assignee: Hitachi, Ltd.Inventors: Hiroshi Miki, Keiko Abdelghafar, Yoshihisa Fujisaki
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Patent number: 6396092Abstract: A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.Type: GrantFiled: September 20, 1999Date of Patent: May 28, 2002Assignee: Hitachi, Ltd.Inventors: Shinichiro Takatani, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki, Kazuyoshi Torii
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Publication number: 20020056862Abstract: The upper electrode of a capacitor is constituted of laminated films which respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.Type: ApplicationFiled: December 27, 2001Publication date: May 16, 2002Inventors: Hiroshi Miki, Keiko Kushida, Yasuhiro Shimamoto, Shinichiro Takatani, Yoshihisa Fujisaki, Hiromi Nakai
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Patent number: 6380574Abstract: A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.Type: GrantFiled: October 31, 2000Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Torii, Yasuhiro Shimamoto, Hiroshi Miki, Keiko Kushida, Yoshihisa Fujisaki
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Publication number: 20020047147Abstract: Disclosed is a semiconductor device having ferroelectric capacitors above a principal surface of a substrate and a process for producing the same wherein an oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier, 61 or 73, under a lower electrode, 62 or 74, of each ferroelectric capacitor formed in the device. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.Type: ApplicationFiled: October 31, 2001Publication date: April 25, 2002Inventors: Keiko Kushida, Masahiko Hiratani, Kazuyoshi Torii, Shinichiro Takatani, Hiroshi Miki, Yuuichi Matsui, Yoshihisa Fujisaki
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Publication number: 20020013006Abstract: A semiconductor memory which is improved in reliability by preventing the lowering of capacitance and defective insulation, especially, electrode delamination. The semiconductor memory has an integrated capacitor composed of a capacitor structure constituted of an upper electrode, a lower electrode, and a capacitor insulating film (of a high-dielectric-constant or ferroelectric thin film) which is held between electrodes and serves as a capacitor insulating film, and a protective insulating film which covers the capacitor structure and is formed by plasma treatment after electrode formation. An oxygen introducing layer is formed on the surface of the capacitor insulating film. The oxygen introducing layer can be formed on the surface of the high-dielectric-constant or ferroelectric material by introducing oxygen to the boundary between the electrode and the material by conducting heat treatment in an oxygen atmosphere before the protective insulating film (SiO2 passivation film) is formed.Type: ApplicationFiled: October 3, 2001Publication date: January 31, 2002Inventors: Hiroshi Miki, Keiko Abdelghafar, Yoshihisa Fujisaki