Patents by Inventor Yoshihisa Nagano
Yoshihisa Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6573111Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mateType: GrantFiled: June 20, 2002Date of Patent: June 3, 2003Assignee: Matsushita Electronics CorporationInventors: Yoshihisa Nagano, Yasuhiro Uemoto, Yuji Judai, Masamichi Azuma, Eiji Fujii
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Patent number: 6562677Abstract: On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture (capacitance determining aperture) formed in the passivation insulating film. The lower electrode, the capacitance insulating film, and the first partial film constitute a capacitance element. The upper electrode has the first partial film which is in contact with the capacitance insulating film and a second partial film which is not in contact with the capacitance insulating film. Since a second electrode wire consisting of a lower-layer film composed of titanium and an upper-layer film composed of an aluminum alloy film is in contact with the second partial film distinct from the first partial film of the upper electrode, titanium or the like encroaching from the second electrode wire can be prevented from diffusing into the capacitance insulating film.Type: GrantFiled: October 13, 2000Date of Patent: May 13, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takumi Mikawa, Yuji Judai, Yoshihisa Nagano
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Patent number: 6528327Abstract: A contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. After that, lower electrode, which will be connected to the contact plug, capacitive insulating film of an insulating metal oxide and upper electrode are formed in this order to make a capacitor.Type: GrantFiled: August 7, 2001Date of Patent: March 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Nagano, Toru Nasu, Hajime Yasuoka, Eiji Fujii
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Patent number: 6528365Abstract: A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen barrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper andType: GrantFiled: October 10, 2001Date of Patent: March 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Nagano, Keisuke Tanaka, Toru Nasu
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Publication number: 20030032230Abstract: A capacitor 11 made up of a lower electrode 8, a capacitive insulating film 9 of an insulating metal oxide and an upper electrode 10 is formed over a semiconductor substrate 1. A first-layer wire 14 is formed on a passivation film 12 that covers the capacitor 11. A first interlevel dielectric film 15 is deposited to cover the first-layer wire 14. A second interlevel dielectric film 17 is deposited over the first interlevel dielectric film 15 with a barrier film 16, which overlaps the capacitor 11 for preventing hydrogen from diffusing, interposed therebetween. A second-layer wire 19 is formed on the second interlevel dielectric film 17. The first interlevel dielectric film 15 has a hydrogen content lower than that of the second interlevel dielectric film 17.Type: ApplicationFiled: June 12, 2002Publication date: February 13, 2003Inventors: Yoshihisa Nagano, Toyoji Ito, Sadayuki Imanishi, Eiji Fujii
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Publication number: 20020195633Abstract: A capacitor includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode. The lower electrode includes a conductive barrier layer that prevents diffusion of oxygen, and an insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode.Type: ApplicationFiled: June 21, 2002Publication date: December 26, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yoshihisa Nagano, Eiji Fujii
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Publication number: 20020179947Abstract: The semiconductor memory device of the present invention includes: an interlayer insulating film formed on a semiconductor substrate; a contact plug formed to extend through the interlayer insulating film; and a capacitor formed on the interlayer insulating film so that an electrode of the capacitor is connected with the contact plug. The electrode has an iridium oxide film as an oxygen barrier film. The average grain size of granular crystals constituting the iridium oxide film is a half or less of the thickness of the iridium oxide film.Type: ApplicationFiled: May 23, 2002Publication date: December 5, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toru Nasu, Yoshihisa Nagano
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Publication number: 20020182802Abstract: A capacitor includes lower electrode, capacitive insulating film, upper electrode and passivation film that are formed in this order on a substrate. The capacitive insulating film is made of an insulating metal oxide, the metal oxide being a ferroelectric or a dielectric with a high relative dielectric constant. At least one contact hole is formed in the passivation film to connect the lower electrode to an interconnect for the lower electrode or the upper electrode to an interconnect for the upper electrode. The opening area of the contact hole is equal to or smaller than 5 &mgr;m2.Type: ApplicationFiled: July 15, 2002Publication date: December 5, 2002Applicant: MATSUSHITA ELECTRONICS CORPORATIONInventors: Keisuke Tanaka, Yoshihisa Nagano, Toyoji Ito, Takumi Mikawa
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Publication number: 20020155663Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mateType: ApplicationFiled: June 20, 2002Publication date: October 24, 2002Inventors: Yoshihisa Nagano, Yasuhiro Uemoto, Yuji Judai, Masamichi Azuma, Eiji Fujii
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Patent number: 6468875Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.Type: GrantFiled: January 24, 2001Date of Patent: October 22, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
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Publication number: 20020149045Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.Type: ApplicationFiled: June 10, 2002Publication date: October 17, 2002Applicant: MATSUSHITA ELECTRONICS CORPORATIONInventors: Yoshihisa Nagano, Yusuhiro Uemoto
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Publication number: 20020149082Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.Type: ApplicationFiled: June 12, 2002Publication date: October 17, 2002Inventors: Yoshihisa Nagano, Toshie Kutsunai, Yuji Judai, Yasuhiro Uemoto, Eiji Fuji
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Patent number: 6448598Abstract: A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.Type: GrantFiled: June 23, 1999Date of Patent: September 10, 2002Assignee: Matsushita Electronics CorporationInventors: Yoshihisa Nagano, Shinichiro Hayashi, Yasuhiro Uemoto
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Patent number: 6441420Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.Type: GrantFiled: May 24, 2000Date of Patent: August 27, 2002Assignee: Matsushita Electronics CorporationInventors: Yoshihisa Nagano, Yasuhiro Uemoto
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Publication number: 20020056861Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.Type: ApplicationFiled: June 24, 1998Publication date: May 16, 2002Inventors: YOSHIHISA NAGANO, TOSHIE KUTSUNAI, YUJI JUDAI, YASUHIRO UEMOTO, EIJI FUJII
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Publication number: 20020029373Abstract: A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen barrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper andType: ApplicationFiled: October 10, 2001Publication date: March 7, 2002Applicant: Matsushita Electronics CorporationInventors: Yoshihisa Nagano, Keisuke Tanaka, Toru Nasu
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Publication number: 20020024079Abstract: A contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. After that, lower electrode, which will be connected to the contact plug, capacitive insulating film of an insulating metal oxide and upper electrode are formed in this order to make a capacitor.Type: ApplicationFiled: August 7, 2001Publication date: February 28, 2002Inventors: Yoshihisa Nagano, Toru Nasu, Hajime Yasuoka, Eiji Fujii
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Publication number: 20020000589Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mateType: ApplicationFiled: November 12, 1998Publication date: January 3, 2002Inventors: YOSHIHISA NAGANO, YASUHIRO UEMOTO, YUJI JUDAI, MASAMICHI AZUMA, EIJI FUJII
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Publication number: 20020000600Abstract: A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.Type: ApplicationFiled: June 23, 1999Publication date: January 3, 2002Inventors: YOSHIHISA NAGANO, SHINICHIRO HAYASHI, YASUHIRO UEMOTO
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Patent number: 6333528Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.Type: GrantFiled: May 4, 1998Date of Patent: December 25, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki