Patents by Inventor Yoshihisa Nagano
Yoshihisa Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8954182Abstract: A robot system includes a manipulator; a work table arranged within a movement extent of the manipulator; an imaging unit for taking a two-dimensional image of the workpieces loaded on the work table; a workpiece supply unit for supplying workpieces onto the work table; and a control system for controlling operations of the manipulator and the imaging unit. The control system includes an imaging control unit for controlling the imaging unit to take the two-dimensional image of the workpieces loaded on the work table, a workpiece detecting unit for detecting a position and a posture of each of the workpieces loaded on the work table by comparing the two-dimensional image taken by the imaging unit with templates stored in advance, and a manipulator control unit for operating the manipulator to perform a work with respect to the workpieces detected by the workpiece detecting unit.Type: GrantFiled: August 30, 2011Date of Patent: February 10, 2015Assignee: Kabushiki Kaisha Yaskawa DenkiInventors: Takeshi Okamoto, Kenji Matsufuji, Takurou Yano, Takuya Murayama, Yoshihisa Nagano
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Publication number: 20150019003Abstract: A robot system according to an aspect of an embodiment includes a robot, a determination unit (work determination unit), a selection unit (chucking direction selection unit), and an instruction unit. The robot has a robot hand (hand) including three or more chuck jaws. The determination unit obtains information on a member formed including a substantially ring shape, and determines a state of the member. The selection unit selects whether to hold the member with the chuck jaws from an inner peripheral side or outer peripheral side based on the determination result of the determination unit. The instruction unit instructs the robot to perform operations of transporting the member while holding the member with the chuck jaws based on the selection result of the selection unit, and assembling a predetermined processed product using the member.Type: ApplicationFiled: October 3, 2014Publication date: January 15, 2015Applicant: KABUSHIKI KAISHA YASKAWA DENKIInventors: Hiroaki MURAKAMI, Ryosuke TSUTSUMI, Kenichi MOTONAGA, Yoshihisa NAGANO
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Patent number: 8887893Abstract: A work system according to embodiments includes a robot and work stations. The robot performs a predetermined work on a workpiece as a work target. The work stations are places where the predetermined work is performed on the workpiece. The robot performs conveying of the workpiece between the work stations.Type: GrantFiled: December 29, 2011Date of Patent: November 18, 2014Assignee: Kabushiki Kaisha Yaskawa DenkiInventors: Ryosuke Tsutsumi, Hiroaki Murakami, Yoshihisa Nagano
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Publication number: 20120217129Abstract: A work system according to embodiments includes a robot and work stations. The robot performs a predetermined work on a workpiece as a work target. The work stations are places where the predetermined work is performed on the workpiece. The robot performs conveying of the workpiece between the work stations.Type: ApplicationFiled: December 29, 2011Publication date: August 30, 2012Applicant: Kabushiki Kaisha Yaskawa DenkiInventors: Ryosuke TSUTSUMI, Hiroaki MURAKAMI, Yoshihisa NAGANO
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Publication number: 20120053724Abstract: A robot system includes a manipulator; a work table arranged within a movement extent of the manipulator; an imaging unit for taking a two-dimensional image of the workpieces loaded on the work table; a workpiece supply unit for supplying workpieces onto the work table; and a control system for controlling operations of the manipulator and the imaging unit. The control system includes an imaging control unit for controlling the imaging unit to take the two-dimensional image of the workpieces loaded on the work table, a workpiece detecting unit for detecting a position and a posture of each of the workpieces loaded on the work table by comparing the two-dimensional image taken by the imaging unit with templates stored in advance, and a manipulator control unit for operating the manipulator to perform a work with respect to the workpieces detected by the workpiece detecting unit.Type: ApplicationFiled: August 30, 2011Publication date: March 1, 2012Applicant: KABUSHIKI KAISHA YASKAWA DENKIInventors: Takeshi OKAMOTO, Kenji Matsufuji, Takurou Yano, Takuya Murayama, Yoshihisa Nagano
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Patent number: 7791119Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.Type: GrantFiled: March 30, 2007Date of Patent: September 7, 2010Assignee: Panasonic CorporationInventors: Akihiro Odagawa, Yoshihisa Nagano
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Patent number: 7781230Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and resistance change characteristics is provided. An electro-resistance element has two or more states in which electric resistance values between a pair of electrodes and is switchable from one of the two or more states into another by applying a predetermined voltage or current between the electrodes.Type: GrantFiled: March 8, 2007Date of Patent: August 24, 2010Assignee: Panasonic CorporationInventors: Akihiro Odagawa, Yoshihisa Nagano
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Patent number: 7776707Abstract: A method includes the steps of: forming a first insulation film on a substrate; forming a hole in the first insulation film; forming a lower electrode on a bottom surface and a sidewall surface of the hole; forming a capacitor insulation film on the lower electrode; forming a second conductive layer on the capacitor insulation film; forming a second insulation film on the second conductive layer so that the second insulation film fills a recess corresponding to the hole; forming a resist mask on the second insulation film so that the resist mask covers the recess; patterning the second insulation film by using the resist mask; and patterning the second conductive layer and the capacitor insulation film by using the patterned second insulation film as a hard mask. By dry etching using a hard mask, a dielectric capacitor having a three-dimensionally stacked structure can be formed with a high yield.Type: GrantFiled: June 5, 2007Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Hiroshi Yoshida, Toyoji Ito, Yoshihisa Nagano
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Patent number: 7531863Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.Type: GrantFiled: November 10, 2005Date of Patent: May 12, 2009Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Nagano, Yasuhiro Uemoto
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Patent number: 7420237Abstract: A capacitor element is provided which is composed of a lower electrode, an upper electrode formed in opposing relation to the lower electrode, and a capacitor dielectric film made of a ferroelectric material or a high dielectric material and formed between the lower and upper electrodes. The lower electrode, the capacitor dielectric film, and the upper electrode are formed in a region extending at least from within a hole provided in an interlayer insulating film having a first hydrogen barrier film disposed on the upper surface thereof toward a position above the hole. A second hydrogen barrier film in contact with the first hydrogen barrier film is disposed to cover the upper surface of the upper electrode and the side surface of the portion of the upper electrode which has been formed above the hole.Type: GrantFiled: January 14, 2005Date of Patent: September 2, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Nagano, Takumi Mikawa
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Publication number: 20070287249Abstract: A method includes the steps of: forming a first insulation film on a substrate; forming a hole in the first insulation film; forming a lower electrode on a bottom surface and a sidewall surface of the hole; forming a capacitor insulation film on the lower electrode; forming a second conductive layer on the capacitor insulation film; forming a second insulation film on the second conductive layer so that the second insulation film fills a recess corresponding to the hole; forming a resist mask on the second insulation film so that the resist mask covers the recess; patterning the second insulation film by using the resist mask; and patterning the second conductive layer and the capacitor insulation film by using the patterned second insulation film as a hard mask. By dry etching using a hard mask, a dielectric capacitor having a three-dimensionally stacked structure can be formed with a high yield.Type: ApplicationFiled: June 5, 2007Publication date: December 13, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroshi YOSHIDA, Toyoji ITO, Yoshihisa NAGANO
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Publication number: 20070246832Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.Type: ApplicationFiled: March 30, 2007Publication date: October 25, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiro ODAGAWA, Yoshihisa Nagano
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Publication number: 20070240995Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and resistance change characteristics is provided. An electro-resistance element has two or more states in which electric resistance values between a pair of electrodes and is switchable from one of the two or more states into another by applying a predetermined voltage or current between the electrodes.Type: ApplicationFiled: March 8, 2007Publication date: October 18, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiro ODAGAWA, Yoshihisa Nagano
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Publication number: 20070235787Abstract: A capacitor device having a three-dimensional structure includes: a lower electrode formed on a semiconductor substrate to have a three-dimensional shape; a capacitor insulating film formed to cover the lower electrode and made of a ferroelectric material; and an upper electrode formed on the capacitor insulating film to have a step portion. A stress control layer is formed on the upper electrode to cause tensile stress and function as a moisture diffusion barrier.Type: ApplicationFiled: April 20, 2006Publication date: October 11, 2007Inventors: Yoshihisa Nagano, Yuji Judai
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Patent number: 7221013Abstract: A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.Type: GrantFiled: August 12, 2004Date of Patent: May 22, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Satoru Goto, Yoshihisa Nagano
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Patent number: 7132709Abstract: A capacitor 11 made up of a lower electrode 8, a capacitive insulating film 9 of an insulating metal oxide and an upper electrode 10 is formed over a semiconductor substrate 1. A first-layer wire 14 is formed on a passivation film 12 that covers the capacitor 11. A first interlevel dielectric film 15 is deposited to cover the first-layer wire 14. A second interlevel dielectric film 17 is deposited over the first interlevel dielectric film 15 with a barrier film 16, which overlaps the capacitor 11 for preventing hydrogen from diffusing, interposed therebetween. A second-layer wire 19 is formed on the second interlevel dielectric film 17. The first interlevel dielectric film 15 has a hydrogen content lower than that of the second interlevel dielectric film 17.Type: GrantFiled: November 2, 2001Date of Patent: November 7, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Nagano, Toyoji Ito, Sadayuki Imanishi, Eiji Fujii
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Patent number: 7053436Abstract: A conductive oxygen barrier layer is formed on an interlayer dielectric film and patterned such that it is in contact with the top surface of a contact plug to prevent the diffusion of oxygen into the contact plug from above. The conductive oxygen barrier layer is composed of a lower layer containing a conductive nitride such as TiAlN, and an upper layer containing a conductive oxide such as IrO2. An insulative oxygen barrier layer composed of Al2O3 and having a thickness of approximately 20 nm is formed on the side surfaces of the conductive oxygen barrier layer to prevent the diffusion of oxygen into the contact plug from the sides, such as from the sides of the lower layer of the conductive barrier layer.Type: GrantFiled: January 8, 2004Date of Patent: May 30, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihisa Nagano, Toshie Kutsunai
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Publication number: 20060065918Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.Type: ApplicationFiled: November 10, 2005Publication date: March 30, 2006Applicant: Matsushita Electronics CorporationInventors: Yoshihisa Nagano, Yasuhiro Uemoto
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Patent number: RE40602Abstract: The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 ?m to 14 ?m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collisions of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.Type: GrantFiled: July 1, 2003Date of Patent: December 9, 2008Assignee: Panasonic CorporationInventors: Akihiro Matsuda, Yoshihisa Nagano, Yasuhiro Uemoto
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Patent number: RE41625Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.Type: GrantFiled: April 22, 2004Date of Patent: September 7, 2010Assignee: Panasonic CorporationInventors: Yoshihisa Nagano, Yasuhiro Uemoto