Patents by Inventor Yoshihisa Sugiura
Yoshihisa Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7848170Abstract: A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value.Type: GrantFiled: March 20, 2009Date of Patent: December 7, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihisa Sugiura
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Publication number: 20100020628Abstract: A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value.Type: ApplicationFiled: March 20, 2009Publication date: January 28, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Yoshihisa SUGIURA
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Patent number: 7636255Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: GrantFiled: September 12, 2007Date of Patent: December 22, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Sugiura, Takashi Suzuki
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Patent number: 7623379Abstract: A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.Type: GrantFiled: March 13, 2007Date of Patent: November 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Inoue, Yoshihisa Sugiura, Tatsuya Tanaka
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Patent number: 7508725Abstract: A semiconductor memory device is disclosed, which includes a memory cell array including a plurality of memory cells, a built-in self-test circuit which writes test pattern data including binary 0 and binary 1 in the memory cells in units of a page to perform a test for the memory cells, a plurality of sense amplifiers which hold a plurality of data read from the memory cells in units of a page, and a detection circuit which collectively detects the plurality of data held by the sense amplifiers and outputs a detection result to the built-in self-test circuit.Type: GrantFiled: January 30, 2007Date of Patent: March 24, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Sugiura, Atsushi Inoue
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Patent number: 7434111Abstract: A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.Type: GrantFiled: April 4, 2005Date of Patent: October 7, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Sugiura, Tatsuya Tanaka, Atsushi Inoue
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Publication number: 20080175057Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: ApplicationFiled: September 12, 2007Publication date: July 24, 2008Inventors: Yoshihisa Sugiura, Takashi Suzuki
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Publication number: 20070245182Abstract: A semiconductor memory device is disclosed, which includes a memory cell array including a plurality of memory cells, a built-in self-test circuit which writes test pattern data including binary 0 and binary 1 in the memory cells in units of a page to perform a test for the memory cells, a plurality of sense amplifiers which hold a plurality of data read from the memory cells in units of a page, and a detection circuit which collectively detects the plurality of data held by the sense amplifiers and outputs a detection result to the built-in self-test circuit.Type: ApplicationFiled: January 30, 2007Publication date: October 18, 2007Inventors: Yoshihisa SUGIURA, Atsushi INOUE
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Patent number: 7277323Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: GrantFiled: June 3, 2005Date of Patent: October 2, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Sugiura, Takashi Suzuki
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Publication number: 20070153582Abstract: A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.Type: ApplicationFiled: March 13, 2007Publication date: July 5, 2007Inventors: Atsushi Inoue, Yoshihisa Sugiura, Tatsuya Tanaka
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Patent number: 7203091Abstract: A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.Type: GrantFiled: April 4, 2005Date of Patent: April 10, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Inoue, Yoshihisa Sugiura, Tatsuya Tanaka
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Publication number: 20060117214Abstract: A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.Type: ApplicationFiled: April 4, 2005Publication date: June 1, 2006Inventors: Yoshihisa Sugiura, Tatsuya Tanaka, Atsushi Inoue
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Publication number: 20060098489Abstract: A semiconductor integrated circuit device includes a non-volatile memory having a pseudo pass function of returning a pass as a status even if a bit error reaching an allowable number of bits occurs after at least one of write or erase sequence is completed. The non-volatile memory includes an issue timing control section for controlling timing of issuing the pseudo pass function.Type: ApplicationFiled: April 4, 2005Publication date: May 11, 2006Inventors: Atsushi Inoue, Yoshihisa Sugiura, Tatsuya Tanaka
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Publication number: 20050213390Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: ApplicationFiled: June 3, 2005Publication date: September 29, 2005Inventors: Yoshihisa Sugiura, Takashi Suzuki
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Patent number: 6914816Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: GrantFiled: October 5, 2004Date of Patent: July 5, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Sugiura, Takashi Suzuki
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Publication number: 20050047207Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: ApplicationFiled: October 5, 2004Publication date: March 3, 2005Inventors: Yoshihisa Sugiura, Takashi Suzuki
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Patent number: 6839276Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: GrantFiled: June 6, 2003Date of Patent: January 4, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihisa Sugiura, Takashi Suzuki
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Patent number: 6801060Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.Type: GrantFiled: May 23, 2003Date of Patent: October 5, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tamio Ikehashi, Yoshihisa Sugiura, Kenichi Imamiya, Ken Takeuchi, Yoshihisa Iwata
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Publication number: 20030227811Abstract: A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.Type: ApplicationFiled: June 6, 2003Publication date: December 11, 2003Inventors: Yoshihisa Sugiura, Takashi Suzuki
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Patent number: D711731Type: GrantFiled: July 16, 2012Date of Patent: August 26, 2014Assignee: Yamaha CorporationInventor: Yoshihisa Sugiura