Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: A memory cell array is divided into left and right cell arrays, each of which includes a plurality of blocks. Data erase is sequentially controlled by an erase control circuit on the basis of an erase command flag incorporated into a command register and an address incorporated into an address register. Batch erase is carried out with respect to selected blocks of the right and left cell arrays. After data erase, a verify operation is carried out with respect to the erased blocks by retrieving the erased blocks simultaneously with respect to the right and left cell arrays in parallel. Thus, the time required to retrieve the selected blocks for the verify operation after data erase is shortened, so that the time required to carry out the whole data erase is shortened.

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.

Abstract: The threshold voltage distribution for write operation into memory cells of a multi-level nonvolatile semiconductor memory device is precisely controlled and the verify result of written data is simultaneously detected for each page. For example, at the "10" data write time, excess write of "00" data which is a conventional problem is inhibited by controlling a path for transferring a lower bit to a bit line according to an upper bit. Further, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the upper bit. At the write time of "01" data, the bit line path is controlled by use of the lower bit and the write operation of "00" data is inhibited. Also, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the lower bit.

Abstract: A potential transfer circuit consists of a first pad, a second pad, a voltage detection circuit, a level shift circuit and a switching MOS transistor. The voltage detection circuit is connected to the first pad and detects a high voltage applied to the first pad and generates a control signal which is supplied to the level shift circuit. The level shift circuit receives the control signal and generates a drive signal which is in turn supplied to the gate of the MOS transistor, causing the MOS transistor to supply to a circuit under test a test signal supplied through the second pad to the drain of the MOS transistor. In preferred embodiments, the power supply of the level shift circuit is derived from the high voltage signal supplied to the first pad.

Abstract: Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.

Abstract: A NOR operation is performed on the address bit by bit by a NOR circuit, and when the final address in a page is detected from the result of the NOR operation by a final address detection circuit, a program starting circuit executes data writing to a memory cell. This can ensure detection of the final address in a page without using a counter circuit. It is therefore possible to simplify the structure of the final address detection circuit and reduce the circuit area occupying in a semiconductor memory device.