Abstract: Each of an image coding apparatus and an image decoding apparatus uses a motion compensated prediction using virtual samples so as to detect a motion vector for each of regions of each frame of an input signal. Accuracy of virtual samples is locally determined while the accuracy of virtual samples is associated with the size of each region which is a motion vector detection unit in which a motion vector is detected. Virtual samples having half-pixel accuracy are used for motion vector detection unit regions having a smaller size 8×8 MC, such as blocks of 8×4 size, blocks of 4×8 size, and blocks of 4×4 size, and virtual samples having ¼-pixel accuracy are used for motion vector detection unit regions that are equal to or larger than 8×8 MC in size.

Abstract: Each of an image coding apparatus and an image decoding apparatus uses a motion compensated prediction using virtual samples so as to detect a motion vector for each of regions of each frame of an input signal. Accuracy of virtual samples is locally determined while the accuracy of virtual samples is associated with the size of each region which is a motion vector detection unit in which a motion vector is detected. Virtual samples having half-pixel accuracy are used for motion vector detection unit regions having a smaller size 8×8 MC, such as blocks of 8×4 size, blocks of 4×8 size, and blocks of 4×4 size, and virtual samples having ¼-pixel accuracy are used for motion vector detection unit regions that are equal to or larger than 8×8 MC in size.

Abstract: A connector is to be attached to a casing. The connector includes a cylindrical body; and a flange extending from the cylindrical body and to be attached to the casing. The flange includes at least one of a depressed section and a cut-out section so that the flange is overlapped with a mating flange at the depressed section or the cut-out section in a thickness direction of the flange.

Abstract: A connector includes a cylindrical body including a latching protrusion and a lance, and a terminal disposed in the cylindrical body. The latching protrusion protrudes from an inner circumferential face of the cylindrical body in a radial direction of the cylindrical body. The lance extends in an axial direction of the cylindrical body in an inclined state relative to the inner circumferential face. The latching protrusion is situated at a position shifted from that of the lance in the axial direction. The terminal includes a holding section at a middle portion thereof in the axial direction, and the holding section includes a first face contacting with the latching protrusion and a second face contacting with the lance.

Abstract: A moving image encoder has an image separating unit (1) for generating four separate images (1)-(4) by sampling pixels constituting an input image every two alternate pixels in the horizontal direction and each alternate pixel in the vertical direction. An intraframe predictive coding unit performs intraframe predictive coding of the separate image (1) by using pixels constituting the separate image (1) produced by the image separating unit (1). An inter-separate image predictive coding unit 12 performs inter-separate image predictive coding of the separate images (2)-(4) produced by the image separating unit 1 by using the pixels constituting the separate image (1) produced by the image separating unit (1).

Abstract: An image encoder includes a preprocessing unit 1 for dividing an image signal into two-dimensional blocks of a prescribed size, and for deciding, for each of the blocks divided, the type of a region to which the block belongs, and generates compressed data by executing, for each block divided by the preprocessing unit 1, coding processing corresponding to the type of the region decided by the preprocessing unit 1. This makes it possible to execute coding processing suitable for each region in a picture, thereby being able to implement an image encoder capable of improving coding efficiency.

Abstract: The present invention provides an illuminating device including a plurality of light-emitting elements arranged in a line, the illuminating device illuminates an irradiation target by irradiating the irradiation target with light that is emitted from the light-emitting elements via a first and a second optical paths. In the illuminating device, a light diffusing portion for diffusing light is provided in one of the first optical path and the second optical path, and an irradiation light amount of said one of the first optical path and the second optical path in which the light diffusing portion is provided is larger than an irradiation light amount of the other optical path.

Abstract: The present invention comprises: an analog/digital conversion means for converting vibration detection signals output from a vibration detection element that detects vibrations of an imaging device into digital signals; a gyro filter that obtains the amount of movement of the imaging device based on the vibration detection signals digitalized by the analog/digital conversion means; a rotation control means for generating an amount of rotary drive in a stepping motor based on both the current position and amount of movement of an optical component or an imaging element; and a stepping control means for generating and outputting pulse signals that drive the rotation of the stepping motor in each phase according to the amount of rotary drive, wherein the stepping control means enables pulse-width modulation of the ratio between the periods in which high-level pulse signals and low-level pulse signals are respectively applied to the same phase of the stepping motor.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: An encoding device includes a color component separating unit for separating an input bit stream for the respective color components, a block dividing unit for dividing an input color component signal into blocks to generate a signal of an encoding unit area, a predicted image generating unit for generating a predicted image for the signal, a determining unit for determining a prediction mode used for encoding according to a prediction efficiency of the predicted image, a prediction error encoding unit for encoding a difference between the predicted image corresponding to the prediction mode determined by the determining unit and the input color component signal, and an encoding unit for variable length-coding the prediction mode, an output from the prediction error encoding unit, and a color component identification flag indicating the color component to which the input bit stream belongs as a result of the color component separation.

Abstract: An illuminating device (210) according to an embodiment of the invention included in an image reading apparatus (100) and an image forming apparatus (D) includes light source portions (211a1), (211b1), (211a2) and (211b2), light-guiding members (213a) and (213b) for illuminating an illumination target (G) from an elongated light emitting face (M) that extends in a longitudinal direction (Y), by guiding light from the light source portions, and holding members (216a) and (216b) for holding the light-guiding members. The holding members include holding portions (2161a) and (2161b) for removably holding the light-guiding members, and tilted portions (2162a) and (2162b) that reflect light emitted from the light emitting face (M), the tilted portions extending from a front end on the light emitting face (M) side of the holding portions, obliquely widening with increasing distance from the light-guiding members.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: Provided are a device and a method for efficiently compressing information by performing improved removal of signal correlations according to statistical and local properties of a video signal in a 4:4:4 format which is to be encoded. The device includes: a prediction unit for determining, for each color component, a motion prediction mode exhibiting a highest efficiency among a plurality of motion prediction modes, and detecting a motion vector corresponding to the determined motion prediction mode, to thereby perform output; and a variable-length encoding unit for determining, when performing arithmetic coding on the motion prediction mode of the each color component, an occurrence probability of a value of the motion prediction mode of the each color component based on a motion prediction mode selected in a spatially-adjacent unit region and a motion prediction mode selected in a temporally-adjacent unit region, to thereby perform the arithmetic coding.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: The invention provides a technique to widely spread the frequency spectrum of switching noise generated by a switching action and to reduce the noise level at a particular frequency. A switching regulator (6A) includes a computing unit with computing function. First, in the computing unit, a pulse-width-modulation processing unit (PWM) (2a) performs pulse-width-modulation processing of receiving a feedback signal corresponding to the output of a detector 1 to determine an on-duty cycle of a pulse signal. Subsequently, for the signal and data obtained by the PWM (2a) to be subjected to further modulation processing for spectrum spreading, a branching processing is performed by making changing-over unit (2d) randomly select asynchronous-modulation processing unit (ASM) (2e) or pulse-position-modulation processing unit (PPM). When the PPM is selected, another branching processing is performed by making the changing-over unit (2d) select a first PPM (2f) or a second PPM (2g) depending on the on-duty cycle.

Abstract: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring in an arithmetic coding process, should be reset in the next transmission unit, an initial register value which indicates a register value to be used to start arithmetic coding/decoding to build/decompose the next transmission unit, only when the register reset flag indicates that the register should not be reset.

Abstract: A node control device is interposed between processor nodes and IO nodes in an information processing system, wherein each IO node subordinates at least one IO device. The node control device includes a register storing a base address of a mapping destination of an IO space, a table describing a plurality of entries retaining a plurality of IO space numbers and address ranges, and an IO space access detection circuit. The table stores an identification flag as to whether or not IO spaces are each mapped onto a memory space. The IO space access detection circuit decodes a command code and an address of an FRTT signal output from a processor node, thus detecting a target IO space and detecting whether the processor node is accessing an IO space mapped onto the memory space or another IO space.