Abstract: A non-volatile memory device includes a data generation circuit and a reconfiguration processing circuit. The data generation circuit generates: third response data that is different from the first response data (PUF registration mode), when the reconfiguration writing is executed by the reconfiguration processing circuit and the first type of challenge data is obtained again after the reconfiguration writing is executed, after the first response data is generated; and fourth response data that is identical to the second response data (permanent PUF registration mode), when the reconfiguration writing is executed by the reconfiguration processing circuit and the second type of challenge data is obtained again after the reconfiguration writing is executed, after the second response data is generated.

Abstract: A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.

Abstract: A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.

Abstract: An authentication apparatus includes: a combination information generator that generates first combination information indicating a combination of physical characteristics of at least two of first elements included in a first semiconductor device; a group identification information generator that generates first group identification information based on the combination of the physical characteristics of the at least two of the first elements, the first group identification information being for identifying the first semiconductor device as belonging to a same group as another semiconductor device manufactured in a same process; a transmitter that transmits the first combination information to an authentication partner; a receiver that receives second group identification information that the authentication partner generates in accordance with the first combination information; and an information verifier that compares the first group identification information with the second group identification information.

Abstract: An image forgery protection apparatus comprises: one or more memories; and circuitry. The circuitry generates challenge data which change with lapse of time at least in a predetermined period. The circuitry generates a unique response which changes with lapse of time, the unique response corresponding to the challenge data on a basis of a physically unclonable function. The circuitry changes subject image data correspondingly to the unique response, the subject image data obtained by capturing an image of a subject.

Abstract: A non-volatile memory device comprises a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

Abstract: A nonvolatile memory device includes: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that includes a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.

Abstract: A data storing method comprises preparing a non-volatile memory device that includes a memory cell array including a plurality of memory cells, wherein the plurality of memory cells include a memory cell in an initial state, which does not change, unless a forming stress is applied thereto, to a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and applying the forming stress to the memory cell in the initial state, to store data in the memory cell array on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a memory array that includes non-volatile memory cells; a read circuit that, in operation, selects, from the memory array, non-volatile memory cells corresponding to one of resistance value ranges, and obtains pieces of resistance value information about resistance values of the selected non-volatile memory cells; a computation circuit that, in operation, calculates a binarization reference value by using the pieces of resistance value information; and an identification information generation circuit that, in operation, generates individual identification information. The read circuit, in operation, obtains first digital data in accordance with relationships between each of the pieces of resistance value information and the binarization reference value.

Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of th

Abstract: An authentication system comprises a host computer; and a non-volatile memory that includes a memory cell array including a plurality of memory cells are arranged in array, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied; and a memory cell in an initial state which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including first authentication data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state, wherein at least one of the host computer an

Abstract: A non-volatile memory device comprises: a memory cell array that includes one or more memory groups each including memory cells, each of the memory cells having variable resistance value to hold a piece of data; a read circuit that, for each of the one or more memory groups, performs a read operation to obtain pieces of time information related to the memory cells in the memory group; and a data generation circuit that generates individual identification information on a basis of order of the memory cells in each of the one or more memory groups, the order corresponding to ascending order or descending order of the pieces of time information related to the memory cells in the memory group. The read circuit obtains each of the pieces of time information on a basis of a discharge phenomenon or charge phenomenon that depends on the resistance value of a corresponding one of the memory cells.

Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.

Abstract: An image forgery protection apparatus comprises: one or more memories; and circuitry. The circuitry generates challenge data which change with lapse of time at least in a predetermined period. The circuitry generates a unique response which changes with lapse of time, the unique response corresponding to the challenge data on a basis of a physically unclonable function. The circuitry changes subject image data correspondingly to the unique response, the subject image data obtained by capturing an image of a subject.

Abstract: A nonvolatile memory device comprises: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that comprising a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.

Abstract: A non-volatile memory device comprises: a memory cell array that includes one or more memory groups each including memory cells, each of the memory cells having variable resistance value to hold a piece of data; a read circuit that, for each of the one or more memory groups, performs a read operation to obtain pieces of time information related to the memory cells in the memory group; and a data generation circuit that generates individual identification information on a basis of order of the memory cells in each of the one or more memory groups, the order corresponding to ascending order or descending order of the pieces of time information related to the memory cells in the memory group. The read circuit obtains each of the pieces of time information on a basis of a discharge phenomenon or charge phenomenon that depends on the resistance value of a corresponding one of the memory cells.

Abstract: An authentication apparatus includes: a combination information generator that generates first combination information indicating a combination of physical characteristics of at least two of first elements included in a first semiconductor device; a group identification information generator that generates first group identification information based on the combination of the physical characteristics of the at least two of the first elements, the first group identification information being for identifying the first semiconductor device as belonging to a same group as another semiconductor device manufactured in a same process; a transmitter that transmits the first combination information to an authentication partner; a receiver that receives second group identification information that the authentication partner generates in accordance with the first combination information; and an information verifier that compares the first group identification information with the second group identification information.

Abstract: A random number processing device according to an aspect of the present disclosure is a random number processing device generating random number data by using data read from memory cells, the memory cells having a property such that, in a variable state, in response to application of different electrical signals, a resistance value of each of the memory cells reversibly transitions between resistance value ranges and, when the resistance value falls within at least one resistance value range among the resistance value ranges, the resistance value changes as time passes, the random number processing device including a random number processing circuit that, in operation, generates first random number data from a combination of first resistance value information and second resistance value information about the resistance values of first and second memory cells among the memory cells which fall within the at least one resistance value range.

Abstract: An encryption and recording apparatus storing data, the apparatus including: a first nonvolatile memory; a second nonvolatile memory; and an encryption and decryption control unit, wherein the encryption and decryption control unit: manages an area included in the second nonvolatile memory on a per-block basis, and manages association between a block and a block-unique key using key management information stored in the first nonvolatile memory; receives the data and corresponding information associated with the data; encrypts the data, using one or more block-unique keys associated with one or more blocks included in the second nonvolatile memory and writes the data to the one or more blocks; and stores the corresponding information into the key management information, associating the corresponding information and the one or more block-unique keys.

Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.