Abstract: A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-re

Abstract: A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a

Abstract: A nonvolatile memory device (300) is provided, including a memory cell array having plural resistance variable elements which are switchable between plural resistance states in response to electric pulses with the same polarity. A series resistance setting unit (310) is provided between the memory cell array (70) and an electric pulse application unit (50). The series resistance setting unit is controlled to change a resistance value of a series current path with a predetermined range with time in at least one of a case where the selected resistance variable element is switched from a low-resistance state to a high-resistance state and a case where the selected resistance variable element is switched from the high-resistance state to the low-resistance state.

Abstract: A variable resistance element (1) whose resistance changes with application of a voltage pulse is brought to a low resistance state by applying an erase pulse to a path shown by the broken line through selection of selection transistors. An erase pulse limiting resistance (2) is inserted in the broken-line path. The resistance value (Re) of the erase pulse limiting resistance (2) is set so that a first resistance value as the sum of all the ON resistance values of the selection transistors, Re and the wiring resistance in the path is equal to or more than a bulk resistance value of a thin film material used in the variable resistance element (1), to prevent the resistance of the variable resistance element (1) from decreasing to the bulk resistance value at which stable resistance change is not resumed.

Abstract: A resistance variable memory apparatus (10) of the present invention comprises a resistance variable element (1) which is switched to a high-resistance state when a voltage exceeds a first voltage and is switched to a low-resistance state when the voltage exceeds a second voltage, a controller (4), a voltage restricting active element (2) which is connected in series with the resistance variable element (1); and a current restricting active element which is connected in series with the resistance variable element (1) via the voltage restricting active element (2), and the controller (4) is configured to control the current restricting active element (3) so that a product of a current and a first resistance value becomes a first voltage or larger and to control the voltage restricting active element (2) so that the voltage between electrodes becomes smaller than a second voltage when the element is switched to the high-resistance state, while the controller (4) is configured to control the current restricting

Abstract: A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a

Abstract: A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-re

Abstract: A variable resistance element (1) whose resistance changes with application of a voltage pulse is brought to a low resistance state by applying an erase pulse to a path shown by the broken line through selection of selection transistors. An erase pulse limiting resistance (2) is inserted in the broken-line path. The resistance value (Re) of the erase pulse limiting resistance (2) is set so that a first resistance value as the sum of all the ON resistance values of the selection transistors, Re and the wiring resistance in the path is equal to or more than a bulk resistance value of a thin film material used in the variable resistance element (1), to prevent the resistance of the variable resistance element (1) from decreasing to the bulk resistance value at which stable resistance change is not resumed.

Abstract: To decrease a space necessary for a layout for mounting an inner shell contained in a shield connector, a shield connector has an upper inner shell and a lower inner shell for electric shield of a cable in the shield connector, wherein a structure for latching operation of respective sidewalls of the upper inner shell and the lower inner shell, the sidewalls being vertically opposed to each other, is configured by a protrusion formed within sheet thickness of one sidewall, and a fitting-in portion which is formed within sheet thickness the other sidewall and formed in such a shape that the protrusion is fitted therein.

Abstract: A reproduction signal 10 is processed in an AD converter 4 and an equalizer 16 to be a decoder input signal 12. The decoder input signal 12 is used to calculate a phase error signal 25 and a quality judgement signal 26. A phase-frequency error detection circuit 22 retains a sign of the phase error signal 25 obtained when the quality judgement signal 26 is changed in quality from “good” to “bad”. The phase-frequency error detection circuit 22 then outputs, as a phase-frequency error signal 27, the phase error signal 25 when the signal quality is “good”, and a given value corresponding to the retained sign when the signal quality is “bad”. A voltage controlled oscillator 9 generates a recovered clock signal 11 whose frequency is based on the oscillation control signal 15 generated by the phase-frequency error signal 27.

Abstract: A reproduction signal 10 is processed in an AD converter 4 and an equalizer 16 to be a decoder input signal 12. The decoder input signal 12 is used to calculate a phase error signal 25 and a quality judgement signal 26. A phase-frequency error detection circuit 22 retains a sign of the phase error signal 25 obtained when the quality judgement signal 26 is changed in quality from “good” to “bad”. The phase-frequency error detection circuit 22 then outputs, as a phase-frequency error signal 27, the phase error signal 25 when the signal quality is “good”, and a given value corresponding to the retained sign when the signal quality is “bad”. A voltage controlled oscillator 9 generates a recovered clock signal 11 whose frequency is based on the oscillation control signal 15 generated by the phase-frequency error signal 27.

Abstract: A reproduction signal 10 is processed in an AD converter 4 and an equalizer 16 to be a decoder input signal 12. The decoder input signal 12 is used to calculate a phase error signal 25 and a quality judgement signal 26. A phase-frequency error detection circuit 22 retains a sign of the phase error signal 25 obtained when the quality judgement signal 26 is changed in quality from “good” to “bad”. The phase-frequency error detection circuit 22 then outputs, as a phase-frequency error signal 27, the phase error signal 25 when the signal quality is “good”, and a given value corresponding to the retained sign when the signal quality is “bad”. A voltage controlled oscillator 9 generates a recovered clock signal 11 whose frequency is based on the oscillation control signal 15 generated by the phase-frequency error signal 27.

Abstract: In order to provide a single-sided, conductor-pinching connector suitable for connecting numerous conductors while reducing occupation space, it comprises an insulating body having a flat male projection extending on its mating side, contact pieces whose contact stems are laid on the opposite surfaces of the flat male projection of the insulating body, a shell enclosing the mating side of the insulating body, and a press plate to press the stripped ends of the insulated conductors against the conductor-pinching rear ends of the contact pieces. The conductor-pinching rear ends are bent at right angle relative to the contact stems of the contact pieces, and are directed in one and same direction. The arranging of upright conductor-pinching ends in one and same direction rather than the opposite directions permits reduction of the connector thickness to possible minimum.