Patents by Inventor Yoshikazu Moriwaki
Yoshikazu Moriwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240304688Abstract: An example apparatus includes a semiconductor substrate having first and second diffusion regions and a channel region arranged between the first and second diffusion regions; a gate electrode covering the channel region with a gate insulating film interposed therebetween; and first and second contact plugs connected to the first and second diffusion regions, respectively. Each of the first and second contact plugs includes an upper section and a lower section arranged between the upper section and an associated one of the first and second diffusion regions. The lower section has a smaller diameter than the upper section at a boundary cross-section between the lower and upper sections.Type: ApplicationFiled: February 14, 2024Publication date: September 12, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: MOEKO KAWANA, YOSHIKAZU MORIWAKI
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Publication number: 20240090206Abstract: A microelectronic device is disclosed, comprising a base structure comprising: active regions individually comprising semiconductor material; and isolation regions horizontally alternating with the active regions and individually comprising insulative material; a transistor structure comprising: a channel within one of the active regions of the base structure and horizontally interposed between two of the isolation regions; a gate dielectric structure including a high-k material above the channel; a gate electrode stack on the gate dielectric structure and comprising: diffusion prevention material on the gate dielectric structure and partially horizontally overlapping the channel, an opening in the diffusion prevention material horizontally centered about a horizontal centerline of the channel and having a smaller horizontal dimension than the channel; a conductive material comprising lanthanum on the diffusion prevention material and substantially filling the opening.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventor: Yoshikazu Moriwaki
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Publication number: 20240081048Abstract: A microelectronic device, comprises a base structure comprising: active regions individually comprising semiconductor material; and isolation regions horizontally alternating with the active regions and individually comprising insulative material; epitaxial semiconductor material on the semiconductor material of one of the active regions, the epitaxial semiconductor material substantially confined within a horizontal area of the one of the active regions and offset from horizontal boundaries of two of the isolation regions horizontally neighboring the one of the active regions; gate dielectric material on the epitaxial semiconductor material, portions of the semiconductor material of the one of the active regions not covered by the epitaxial semiconductor material, and portions of the two of the isolation regions; and a gate electrode stack on the gate dielectric material.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Yuri Ishizaki, Yoshikazu Moriwaki
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Publication number: 20240072138Abstract: A variety of applications can include apparatus having one or more transistors with a contact arrangement to significantly mitigate a parasitic capacitance between one or more contacts to an active area of the transistor and a gate of the transistor. One or more contact arrangements can include a contact to an active area in a position beyond a boundary of an end of the gate along a first direction, where the gate is structured along the first direction. One or more other contact arrangements can include two contacts to an active area in positions beyond boundaries of two opposite ends of the gate along a first direction. Arrangements can include a metal silicide region coupling two contacts to each other in an active region with the two contacts in positions beyond boundaries of two opposite ends of the gate along a first direction.Type: ApplicationFiled: August 15, 2023Publication date: February 29, 2024Inventor: Yoshikazu Moriwaki
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Publication number: 20240014289Abstract: Apparatuses including a semiconductor transistor and methods for forming same are described. An example apparatus includes an active region in a semiconductor substrate, an isolation region configured to isolate the active region, and a gate structure on the active region. The isolation region includes a dielectric material with an addition of a metal material in the dielectric material. The gate structure has portions overlapping the isolation region. The gate structure includes a gate, and further includes a gate insulator that includes a film of the metal material and is disposed between the active region and the gate.Type: ApplicationFiled: July 5, 2022Publication date: January 11, 2024Applicant: MICRON TECHNOLOGY, INC.Inventor: Yoshikazu Moriwaki
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Patent number: 11843035Abstract: Semiconductor devices including structures of active region are disclosed. An example semiconductor device according to the disclosure includes a substrate, a layer on the substrate and a dielectric layer on the layer. The layer includes an interface in contact with the dielectric layer. The interface includes a first portion on a surface of the layer and a second portion perpendicular to the first portion.Type: GrantFiled: December 21, 2020Date of Patent: December 12, 2023Assignee: Micron Technology, Inc.Inventors: Moeko Kawana, Yoshikazu Moriwaki
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Publication number: 20230317823Abstract: A semiconductor structure includes a first sidewall spacer on sidewalls of a first device structure on a surface of a substrate and a second sidewall spacer on sidewalls of a second device structure on the surface of the substrate. The first sidewall spacer includes a first liner layer on sidewalls of the first device structure, a first oxide spacer on the first liner layer and on the surface of the substrate, and a first etch stop layer on the first oxide spacer. The second sidewall spacer includes a second liner layer on sidewalls of the second device structure, an inner oxide spacer on the second liner layer and on the surface of the substrate, a second etch stop layer on the inner oxide layer, and an outer oxide spacer on the second etch stop layer.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Micron Technology, Inc.Inventors: Kehan Zhang, Yoshikazu Moriwaki
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Patent number: 11769765Abstract: Apparatuses with a gate electrode in a semiconductor device are described. An example apparatus includes an active region, an isolation region surrounding the active region, a dielectric layer including a first portion above the active region and a second portion above the isolation region, and a protection layer on the isolation region.Type: GrantFiled: March 15, 2021Date of Patent: September 26, 2023Assignee: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Patent number: 11527536Abstract: Semiconductor devices including structures of gate electrode layers are disclosed. An example semiconductor device according to the disclosure includes a semiconductor substrate and first and second gate electrodes above the semiconductor substrate. Each gate electrode of the first and second gate electrodes includes a gate insulator above the semiconductor substrate, a first gate electrode layer on the gate insulator, and a second gate electrode layer on the first gate electrode layer. The second gate electrode layers of the first and second gate electrodes have impurity concentrations that are different from one another.Type: GrantFiled: January 7, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Mika Yoshida, Yoshikazu Moriwaki
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Publication number: 20220293582Abstract: Apparatuses with a gate electrode in a semiconductor device are described. An example apparatus includes an active region, an isolation region surrounding the active region, a dielectric layer including a first portion above the active region and a second portion above the isolation region, and a protection layer on the isolation region.Type: ApplicationFiled: March 15, 2021Publication date: September 15, 2022Applicant: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Publication number: 20220216206Abstract: Semiconductor devices including structures of gate electrode layers are disclosed. An example semiconductor device according to the disclosure includes a semiconductor substrate and first and second gate electrodes above the semiconductor substrate. Each gate electrode of the first and second gate electrodes includes a gate insulator above the semiconductor substrate, a first gate electrode layer on the gate insulator, and a second gate electrode layer on the first gate electrode layer. The second gate electrode layers of the first and second gate electrodes have impurity concentrations that are different from one another.Type: ApplicationFiled: January 7, 2021Publication date: July 7, 2022Applicant: Micron Technology, Inc.Inventors: Mika Yoshida, Yoshikazu Moriwaki
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Publication number: 20220199779Abstract: Semiconductor devices including structures of active region are disclosed. An example semiconductor device according to the disclosure includes a substrate, a layer on the substrate and a dielectric layer on the layer. The layer includes an interface in contact with the dielectric layer. The interface includes a first portion on a surface of the layer and a second portion perpendicular to the first portion.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Applicant: Micron Technology, Inc.Inventors: Moeko Kawana, Yoshikazu Moriwaki
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Patent number: 10490645Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.Type: GrantFiled: August 14, 2018Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Publication number: 20190027412Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.Type: ApplicationFiled: August 14, 2018Publication date: January 24, 2019Applicant: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Patent number: 10115642Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.Type: GrantFiled: February 9, 2018Date of Patent: October 30, 2018Assignee: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Publication number: 20180174926Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.Type: ApplicationFiled: February 9, 2018Publication date: June 21, 2018Applicant: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Patent number: 9922885Abstract: Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.Type: GrantFiled: November 30, 2016Date of Patent: March 20, 2018Assignee: Micron Technology, Inc.Inventor: Yoshikazu Moriwaki
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Publication number: 20160064285Abstract: On a peripheral circuit area upon a semiconductor substrate, an NMOS gate stack, comprising a first high-dielectric film, an NMOS gate metal, and a first semiconductor film, is formed, and a PMOS gate stack, comprising a second high-dielectric film, a PMOS gate metal, and a second semiconductor film, is formed so that a predetermined step is formed between the NMOS gate stack and the PMOS gate stack. A third semiconductor film is formed over the entire surface of the semiconductor substrate so as to fill in the step. The third semiconductor film is planarized by way of CMP so as to form a fourth semiconductor film that is thinner than the third semiconductor film.Type: ApplicationFiled: March 20, 2014Publication date: March 3, 2016Inventor: Yoshikazu MORIWAKI
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Publication number: 20160027778Abstract: One semiconductor device includes a first active region provided on a semiconductor substrate in which a transistor having a high dielectric constant gate insulating film, a gate electrode, and a diffusion layer is disposed, an element separation region that is in contact with and surrounds the first active region, and a dummy active region that is in contact with the element separation region.Type: ApplicationFiled: March 10, 2014Publication date: January 28, 2016Inventors: Yoshikazu Moriwaki, Kanta Saino
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Publication number: 20140197495Abstract: A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.Type: ApplicationFiled: March 18, 2014Publication date: July 17, 2014Applicant: Elpida Memory, Inc.Inventor: Yoshikazu MORIWAKI