Abstract: There is provided a condenser state predicting device capable of recognizing operating condition-based state prediction information regarding the performance of a condenser and the thickness reduction of its tubes. A condenser state predicting device of an embodiment includes a display information generator configured to generate at least one of: first screen display information to display performance information indicating performance of a condenser, the performance of the condenser being predicted based on measurement information that is measured or input information that is input; and second screen display information to display residual thickness information indicating a residual ratio of the thickness of tubes of the condenser, the residual ratio being predicted based on the input information.

Abstract: A memory system includes a first die, a second die, and a controller that controls writing and reading of data to and from the first die and the second die. The first die includes a first nonvolatile memory and a first volatile memory, and the second die includes a second nonvolatile memory and a second volatile memory. The controller includes a third volatile memory and during writing of data into the first die, the controller writes the data, which is stored in the third volatile memory and is to be stored in the first die, to the first volatile memory of the first die and the second volatile memory of the second die in parallel.

Abstract: A memory system includes a semiconductor storage device and a memory controller for the semiconductor storage device. The semiconductor storage device includes a plurality of blocks including a plurality of memory cell transistors. The plurality of blocks includes a first block and a second block. The memory cell transistor in the first block stores data having a first number of bits during a first period and stores data having a second number of bits larger than the first number during a second period that begins after the first period ends.

Abstract: A memory system includes a semiconductor storage device and a memory controller for the semiconductor storage device. The semiconductor storage device includes a plurality of blocks including a plurality of memory cell transistors. The plurality of blocks includes a first block and a second block. The memory cell transistor in the first block stores data having a first number of bits during a first period and stores data having a second number of bits larger than the first number during a second period that begins after the first period ends.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first circuit, and a second circuit. The first circuit executes program and read. The program is processing for changing a threshold voltage of a memory cell to a voltage according to data. The data includes first data of a bit and second data of a bit. The program of the second data is executed after the program of the first data. The read includes measuring the threshold voltage. The second circuit manipulates a flag in accordance with execution of the program of the second data. In a case where the second data is a target of the read, the second circuit refers to the flag. In a case where the flag indicates non-execution of the program of the second data, the second circuit aborts the measuring before the measuring of the threshold voltage is completed.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, a semiconductor memory device includes: memory cells; word lines electrically connected to gates of the memory cell; and an interconnect electrically connected to one end of the memory cells. A first potential for applying to a selected memory cell in a read operation is determined based on a potential of the interconnect during sequentially increasing or decreasing a potential of the word line.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.

Abstract: According to one embodiment, a controller switches modes including a normal operating mode in which power resources of a volatile memory, a data storage unit, and a power control unit are all ON, a first mode in which the power resource of the volatile memory is OFF, and the power resources of the data storage unit and the power control unit are both ON, and a second mode in which the power resources of the volatile memory and the data storage unit are both OFF, and the power resource of the power control unit is ON. Upon receiving a low power consumption instruction command from a host, the controller stores management information to return to the normal operating mode into the volatile storage unit, and shifts the state of the memory system from the normal operating mode to the first mode.

Abstract: According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.