Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

Abstract: A memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system includes a controller writing to the memory cells in a number of bits in accordance with a write request of a host, dividing the memory cells into groups in dependence on storage capacity after the numbers of rewrites of the memory cells managed by the number-of-rewrites management table exceed a specified number, and writing to the memory cells of the group corresponding to storage capacity of the number of bits in accordance with the write request of the host.

Abstract: According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode.

Abstract: According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode.

Abstract: According to one embodiment, a memory system includes nonvolatile memory having a plurality of memory cells of storage capacity of a specified number of bits equal to or greater than two bits, and a number-of-rewrites management table managing numbers of rewrites of the memory cells. The memory system of the embodiment includes a controller writing to the memory cells in a number of bits in accordance with a write request of a host, dividing the memory cells into groups in dependence on storage capacity after the numbers of rewrites of the memory cells managed by the number-of-rewrites management table exceed a specified number, and writing to the memory cells of the group corresponding to storage capacity of the number of bits in accordance with the write request of the host.

Abstract: According to one embodiment, a memory system includes a NAND flash memory includes a memory cell array includes pages, and a volatile data register with a storage capacity of one page, and configured to write page data to the memory cell array through the data register, each of the pages includes nonvolatile memory cells and being a unit of data write, a volatile RAM, and a controller includes a power saving mode in which power consumption of the RAM is reduced, and configured to transfer data of the RAM to the data register before entering the power saving mode.

Abstract: A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.

Abstract: A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.

Abstract: A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Abstract: A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit.

Abstract: The disclosure concerns a power supply circuit comprising a voltage converter receiving an external voltage and outputting an internal voltage; a first switch and a second switch connected between an output of the voltage converter and a constant voltage source; a resistor provided between the first switch and the second switch, and dividing the internal voltage; a comparator including a first input unit, a second input, and an output which is connected to the voltage converter; a reference voltage source supplying a reference voltage to the first input; a feedback feeding back a voltage divided by the resistor to the second input from a node between the first switch and the second switch; a setting voltage source, to the second input; a third switch connected between the setting voltage source and the second input; and a control signal generator controlling the first switch, the second switch, and the third switch.

Abstract: A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Abstract: A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.

Abstract: A power source circuit that outputs a designated voltage through an output terminal thereof, comprising: a step-up circuit that steps up a voltage fed from a power supply and applies the resultant voltage to the output terminal; a voltage sensing circuit that senses a voltage outputted from the step-up circuit and outputs a signal with which activation of the step-up circuit is controlled; and a filter circuit that includes a variable resistor connected between the output side of the step-up circuit and the output terminal.

Abstract: A memory cell array includes a plurality of memory cells in each of which a plurality of bits are stored. A sense amplifier detects data read from a memory cell selected from the memory cell array. At the time of a write verify operation for verifying write data, when a threshold voltage of the memory cell exceeds a predetermined checkpoint, the data control unit converts write data to be written to the memory cell into data of the number of times indicating the remaining number of write voltage application times, inverts only one bit of the data of the number of times each time a write voltage application operation is performed, and changes a definition of the data of the number of times to thereby perform a subtraction operation.

Abstract: A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.

Abstract: A voltage supply circuit that switches and outputs multiple set voltages from an output terminal, has a boosting circuit that boosts a voltage supplied from a power supply and outputs the voltage to the output terminal; a voltage detecting circuit that outputs a first flag signal when detecting that the voltage outputted from the boosting circuit is not lower than the set voltage, outputs a second flag when detecting that the voltage outputted from the boosting circuit is not lower than a frequency adjusting voltage set lower than the set voltage; and a control circuit that controls an operation of the boosting circuit in response to the set voltage and the output signal of the voltage detecting circuit.

Abstract: A power supply circuit, comprises a booster circuit that boosts the voltage supplied from a power supply to produce an output voltage; a voltage divider circuit that divides said output voltage by resistive division and outputs a monitored voltage; a comparator circuit that compares said monitored voltage with a reference voltage and outputs a signal to activate said booster circuit if said monitored voltage is lower than said reference voltage and a signal to deactivate said booster circuit if said monitored voltage is higher than said reference voltage; an auxiliary instruction circuit that outputs an auxiliary signal to control the timing of the activation of said booster circuit; and an arithmetic circuit that performs a calculation using said auxiliary signal and the output signal of said comparator circuit and outputs an enable signal to activate said booster circuit if the output signal of said comparator circuit is a signal to activate said booster circuit, or said auxiliary signal is a signal to acti