Abstract: A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Abstract: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters comprising memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

Abstract: This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.