NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters.
This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 2006-199673 filed in Japan on Jul. 21, 2006, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTIONThe present invention relates to a non-volatile semiconductor storage device which can be electrically erased and written, to a state determination method for such a semiconductor storage device, and to a semiconductor integrated circuit device incorporating such a semiconductor storage device.
Along with increase of internal SRAM capacity, the necessity has increased for providing redundancy, for performing individual tuning after making boards such as LCD drivers and the like, and for low cost fuses which are being demanded along with the great increase in various types of application which involve personal identification information (ID codes, encryption and decryption keys, numbers of IC cards, and the like).
In the prior art, as fuse elements which can be made with a standard CMOS process, there is a known one in which a polysilicon or metal wiring layer is blown out by a laser or an electrical current, a known one in which an insulating gate layer or the like is destroyed by voltage, and the like. However, such a fuse which employs such a blowing out or insulation destruction method or the like is not suitable for the application described above, since it can only be programmed once.
On the other hand, in the case of using a non-volatile element of the floating gate type which can be manufactured by a CMOS process, although it is possible to implement a fuse which can be electrically erased and written, introduction of a special process for making the transistors non-volatile, such with a prior art type flash memory, is not appropriate from the point of view of cost. Furthermore, with a floating gate type element made with a standard CMOS process, there has been the problem that the data storage characteristics deteriorate as the insulating layer becomes thinner along with increase of the integration scale.
Thus in, for example, U.S. Pat. No. 6,518,614, Japanese Laid-Open Patent Publication 2004-56095, and Japanese Laid-Open Patent Publication 2005-353106, there are disclosed a non-volatile storage device which can be manufactured by a standard CMOS process, and a non-volatile storage device which does not have any special floating gates.
While the operation of such a memory cell is as described above, there are the following problems with this structure.
(1) The margin of threshold voltage difference is small.
Vth1−Vth0 corresponds to this threshold voltage difference margin in the case of the data “0”, and Vth2−Vth1 in the case of the data “1”. To some extent, there is an upper limit value Vth_max for the amount of change of the threshold voltage due to the hot carrier injection phenomenon. If the margin is allocated equally between reading out the data “0” and the data “1”, then, if it is supposed that rewriting is performed once, the margin for each becomes (Vth_max−Vth0)/2. And, if it is supposed that rewriting is performed N times, then taking the maximum value of Vth_control as Vth_max, it must be divided into 2N portions, and the margin of each of the data “0” and the data “1” becomes (Vth_max−Vth0)/2N, so that the margin becomes yet smaller.
(2) As operating voltages when writing data into this non-volatile data storage unit, it is necessary to apply high voltages (7 V and 5 V) to the word line WL and to the bit lines BLT and BLB for each memory cell which it is necessary to control. This means that it is necessary to use high withstand voltage transistors for the drivers which drive the word lines and the bit lines, and for the column selection transistors for selecting the bit lines. Since the performance with high withstand voltage transistors, which are optimized for high voltage, is deteriorated when operating at Vcc=1.8 V as during normal reading out operation, accordingly the problem occurs that this entails access delay. And increasing the size of the transistors in order to increase the current drive capability causes the accompanying problem that the chip area becomes large.
One object of the present invention is to provide a rewritable non-volatile semiconductor storage device, with which it is possible to make the reading out margin large.
A further object of the present invention is to provide a rewritable non-volatile semiconductor storage device, with which it is possible to perform control of the word lines and the bit lines at the Vcc level.
Other objects of the present invention are to provide a state determination method for such a semiconductor storage device, and to provide a semiconductor integrated circuit device incorporating such a semiconductor storage device.
SUMMARY OF THE INVENTIONThe non-volatile semiconductor storage device of the present invention includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of said flip-flop on a side thereof.
Furthermore, the non-volatile semiconductor storage device of the present invention includes two bit lines, each of which is connected to a respective one of said two gate transistors, and a word line which is connected to both of the gate electrodes of said two gate transistors. These two bit lines and this word line are controlled to a voltage between operating power supply voltage and ground voltage.
Moreover, the non-volatile semiconductor storage device of the present invention includes a first voltage supply line which is connected to the sources of said storage transistors of said inverters, and a second voltage supply line which is connected to the sources of said load transistors of said inverters. A predetermined first voltage is supplied to the first voltage supply line during writing and during erasure. And a predetermined second voltage is supplied to the second voltage supply line during writing. This predetermined first voltage and this predetermined second voltage may be, for example, high voltages greater than or equal to the operating power supply voltage.
These storage transistors are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. In the non-volatile semiconductor storage device described above, the writing and erasure of data are implemented by controlling the threshold voltages of the storage transistors. These threshold voltages are provided via the first voltage supply line and the second voltage supply line which are connected to the two ends of the two inverters (the sources of the load transistors and the sources of the storage transistors).
Accordingly, when performing writing by elevating the threshold voltage of a first one of the storage transistors, and when performing erasure by lowering the threshold voltage of this first one of the storage transistors, this may be performed by the word lines and the bit lines operating at the level of the operating power supply voltage (Vcc). For this, in the above described non-volatile semiconductor storage device which makes it possible for peripheral circuitry to be more compact and be read out at higher speed, each of the storage transistors further includes an insulation layer side spacer which is formed at a side portion of its gate electrode; and a low impurity density region which is formed at a border portion of its drain.
During writing, said first voltage supply line applies said first voltage to the sources of said storage transistors, and said second voltage supply line applies said second voltage to the gates of said storage transistors via the sources of said load transistors; and thereby information is written into said storage transistors by channel hot electrons being injected into said insulation layer side spacer.
And, during erasure, said first voltage supply line applies said first voltage to the sources of said storage transistors; and thereby erasure of information which is stored in said storage transistors is performed by an avalanche of hot holes being injected into said insulation layer side spacer.
The above described first voltage and second voltage are high voltages which are greater than Vcc.
A non-volatile storage device according to a first embodiment of the present invention, and a semiconductor integrated circuit device which incorporates it, will now be explained with reference to
In this flip-flop, the inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the true side, while the inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the bar side. The connection portion between the load transistor MP1 and the storage transistor MCN1 is a node T, while the connection portion between the load transistor MP2 and the storage transistor MCN2 is a node B. When the node T is at high potential and the node B is at low potential, the stored contents is “0”; while, when the node T is at low potential and the node B is at high potential, the stored contents is “1”.
The storage transistor side end portions of these inverters, in other words the sources of the storage transistors MCN1 and MCN2, are connected to a source line SL (a supply line for a first voltage). And the load transistor side end portions of these inverters, in other words the sources of the load transistors MP1 and MP2, are connected to a VPS line (a supply line for a second voltage). Furthermore, the wells of the load transistors MP1 and MP2 are connected to a VPM line.
The node T is connected to a bit line BLT (Bit Line-True) via a transfer gate MN1, while the node B is connected to a bit line BLB (Bit Line-Bar) via a transfer gate MN2. The transfer gates MN1 and MN2 are N-type MOS transistors, and a common word line WL is connected to both of these gates.
In
This storage transistor is an N-channel type transistor, and comprises, on the surface region of the P-type well 104, a drain 109 and a source 115 which are formed adjacent to the trenches 102 on the two sides, and a drain extension 107 which is formed in a region adjacent to the drain 109. The drain 109 and the source 115 are formed with an average arsenic density of 1·1020 cm−3, and the drain extension 107 is formed with an average arsenic density of 5·1018 cm−3.
Furthermore, upon the substrate in the channel region, which is the region of the surface of the P-type well 104 between the drain 109 and the source 115, there are formed a gate oxide layer 105 of thickness 5 nm, and a gate electrode 106 which is made from a polysilicon layer of thickness 200 nm and having a phosphorus density of 2·1020 cm−3. Furthermore, on both sides of this gate oxide layer 105 and gate electrode 106, there are formed side spacers 108 which are made as insulating layers of thickness 50 nm. It should be understood that the side spacer 108S on the source side is exposed to the channel region of the substrate, since no extension region is formed around the periphery of the source 115.
Furthermore, within the region of the P-type well 104, a P-type diffusion layer 111 having an average boron density of 1·1020 cm−3, which is an electrode for grounding this P-type well, is formed in a region which is separated from the storage transistor described above by one of the trenches 102.
With this storage transistor, the threshold voltage can be elevated by injecting carriers into the side spacer 108S on the source side. Furthermore, as will be explained with reference to
It should be understood that, although the initial threshold voltage of this storage transistor is 1.2 V, the variation is great since it is a transistor of a distinctive structure, and accordingly, from the point of view of reliability, it is not possible to utilize such a storage transistor singly as a storage element. Because of this, in this embodiment, the memory cell is built with the flip-flop structure shown in
In
In order to bring the storage transistor MCN1 to this potential configuration, voltages are applied to the memory cell in the condition shown in
Furthermore, when writing the data “1”, while the threshold voltage on the side of the storage transistor MCN2 becomes elevated, the other conditions are the same as when writing the data “0”, with only the voltage settings for BLT=Vcc and BLB=0 V being reversed.
It should be understood that although, in the embodiment described above, 6V was applied to the gate of the transistor MCN1 (the node B), and 6V was also applied to the source of the transistor MCN1 (the source line SL), it would also be acceptable for these voltages to be different voltages.
In the actual memory cell, these voltages are applied under the conditions shown in
Since, in this manner, with the voltage application conditions during writing as shown in
And
When the erase operation explained with reference to
Since, in this manner, the structure is arranged so that, even though the threshold voltages of the storage transistors MCN1 and MCN2 have once been raised, it is still possible again to lower them to the initial state Vth0, accordingly, even though requests for rewriting of the data have been issued a number of times, it is still possible to obtain a sufficient margin for reading out, which is the difference between the threshold voltages on the true side (the storage transistor MCN1) and on the bar side (the storage transistor MCN2).
With this six transistor non-volatile memory cell of the first embodiment, in the state in which writing has not been performed, in other words in the state in which the threshold voltages of the storage transistors MCN1 and MCN2 are both low, the data is indeterminate. Thus, as shown in
The non-volatile memory cell shown in
When the power supply to the memory cell having this structure is turned ON in the state in which neither one of the storage transistors MCN1 and MCN2 has been written, the potential at the node T rises faster than that at the node B, and the load transistor MP1 and the storage transistor MCN2 go into the ON state, while the load transistor MP2 and the storage transistor MCN1 go into the OFF state; in other words, the data stabilizes at “0”.
It should be understood that, instead of unbalancing the channel widths as described above, it would also be acceptable to unbalance the channel lengths. Furthermore, it would also be acceptable for the load transistor whose channel width or channel length is changed to be either MP1 or MP2. Moreover, it would also be acceptable to perform this unbalancing by changing the channel width or the channel length of one of the storage transistors MCN1 or MCN2.
On the other hand, the non-volatile memory cell shown in
Due to this, when the power supply is turned ON in the state in which neither writing nor erasure of either of the two storage transistors MCN1 and MCN2 has been performed, since the potential of the node T rises quickly directly after the power supply has been turned ON while the potential of the node B rises more slowly, accordingly the system stabilizes with the load transistor MP1 and the storage transistor MCN2 in the ON state and the load transistor MP2 and the storage transistor MCN1 in the OFF state, in other words at the data “0”.
Although, in the example shown in
A non-volatile storage device according to a second embodiment of the present invention, and a semiconductor integrated circuit device which incorporates it, will now be explained with reference to
The storage transistor side end portions of these inverters, in other words the sources of the storage transistors MCN1 and MCN2, are connected to a source line SL. And the load transistor side end portion of the true side inverter, in other words the source of the load transistor MP1, is connected to a line VPST, while the load transistor side end portion of the bar side inverter, in other words the source of the load transistor MP2, is connected to a line VPSB.
In this flip-flop, the inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the true side, while the inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the bar side. The connection portion between the load transistor MP1 and the storage transistor MCN1 is a node T, while the connection portion between the load transistor MP2 and the storage transistor MCN2 is a node B. When the node T is at high potential and the node B is at low potential, the stored contents is “0”; while, when the node T is at low potential and the node B is at high potential, the stored contents is “1”.
The node T is connected to a bit line BLT (Bit Line-True) via a transfer gate MN1, while the node B is connected to a bit line BLB (Bit Line-Bar) via a transfer gate MN2. The transfer gates MN1 and MN2 are N-type MOS transistors, and a common word line WL is connected to both of these gates.
Furthermore a P-type MOS transistor MP3, which is a transistor for pre-charge, is connected in parallel with the load transistor MP1, in other words between the node T and VPST. Moreover a P-type MOS transistor MP4, which also is a transistor for pre-charge, is connected in parallel with the load transistor MP2, in other words between the node B and VPSB. A T-side pre-charge line PRET is connected to the gate of the P-type MOS transistor MP3, while a B-side pre-charge line PREB is connected to the gate of the P-type MOS transistor MP4. Furthermore, all of the P-type MOS transistors MP1 through MP4 are formed within the same N well, and the potential of this N well is controlled by a signal VPM.
This storage transistor is an N-channel type transistor, and comprises, on the surface region of the P-type well 104, a drain 109 and a source 115 which are formed adjacent to the trenches 102 on the two sides, and a drain extension 107 which is formed in a region adjacent to the drain 109. The drain 109 and the source 115 are formed with an average arsenic density of 1·1020 cm3, and the drain extension 107 is formed with an average arsenic density of 5·1018 cm−3.
Furthermore, upon the substrate in the channel region, which is the region of the surface of the P-type well 104 between the drain 109 and the source 115, there are formed a gate oxide layer 105 of thickness 5 nm, and a gate electrode 106 which is made from a polysilicon layer of thickness 200 nm and having a phosphorus density of 2·1020 cm−3. Furthermore, on both sides of this gate oxide layer 105 and gate electrode 106, there are formed side spacers 108 which are made as insulating layers of thickness 50 nm. It should be understood that the side spacer 108S on the source side is exposed to the channel region of the substrate, since no extension region is formed around the periphery of the source 115.
Furthermore, within the region of the P-type well 104, a P-type diffusion layer 111 having an average boron density of 1·1020 cm−3, which is an electrode for grounding this P-type well, is formed in a region which is separated from the storage transistor described above by one of the trenches 102.
With this storage transistor, the threshold voltage can be elevated by injecting carriers into the side spacer 108S on the source side. Furthermore, as will be explained with reference to
It should be understood that, although the initial threshold voltage of this storage transistor is 1.2 V, the variation is great since it is a transistor of a distinctive structure, and accordingly, from the point of view of reliability, it is not possible to utilize such a storage transistor singly as a storage element. Because of this, in this embodiment, the memory cell is built with the flip-flop structure shown in
In
In order to bring the storage transistor MCN1 to this potential configuration, voltages are applied to the memory cell in the condition shown in
Furthermore, when writing the data “1”, while the threshold voltage on the side of the storage transistor MCN2 becomes elevated, the other conditions are the same as when writing the data “0”, with only the voltage settings for BLT=Vcc and BLB=0 V being reversed.
It should be understood that although, in the embodiment described above, 6V was applied to the gate of the transistor MCN1 (the node B), and 6V was also applied to the source of the transistor MCN1 (the source line SL), it would also be acceptable for these voltages to be different voltages.
In the actual memory cell, these voltages are applied under the conditions shown in
Since, in this manner, with the voltage application conditions during writing as shown in
And
When the erase operation explained with reference to
Since, in this manner, the structure is arranged so that, even though the threshold voltages of the storage transistors MCN1 and MCN2 have once been raised, it is still possible again to lower them to the initial state Vth0, and furthermore since it is possible forcibly to determine the storage transistors MCN1 and MCN2 to the data “1”, even if they are both in the initial state Vth0, accordingly, even though requests for rewriting of the data have been issued a number of times, it is still possible to obtain a sufficient margin for reading out, which is the difference between the threshold voltages on the true side (the storage transistor MCN1) and on the bar side (the storage transistor MCN2).
By the writing operation shown in
The procedure shown in
At the time instant T2, PRET and PREB return to Vcc, and, from the time instant T3, the source potential SL slowly drops towards 0 V. At this time, if the storage contents of the memory cell is “1”, then, since the transistor MCN1 whose threshold voltage is the lower goes to ON before the transistor MCN2, accordingly the node T is pulled down to 0 V first while the node B goes to Vcc, so that the data of the flip-flop is determined at “1”. On the other hand, if the storage contents of the memory cell is “0”, then, since likewise the threshold voltage of the transistor MCN2 is lower than the threshold voltage of the transistor MCN1 (even though its threshold voltage is elevated by just ΔV) so that the storage transistor MCN2 goes to ON first, accordingly the node B is pulled down to 0 V first while the node T goes to Vcc, so that the data of the flip-flop is determined at “0”.
Furthermore, if the storage contents of the memory cell is “indeterminate”, in other words if the threshold voltages of both the transistors MCN1 and MCN2 are Vth0, then, since the apparent threshold voltage of the storage transistor MCN1 is just ΔV lower than the threshold voltage of the storage transistor MCN2, accordingly the transistor MCN1 goes ON before the transistor MCN2, and the node T is pulled down to 0 V first while the node B goes to Vcc, so that the data of the flip-flop is determined at “1”.
VPST is returned to Vcc at a time instant T4 after the state of the flip-flop is determined.
Since often a memory cell in which the threshold voltages of MCN1 and MCN2 are both Vth0 is a cell to which, up till now, neither writing nor rewriting has been performed, and since, with this type of memory cell, the transistors do not deteriorate along with rewriting, accordingly, with regard to the setting of ΔV, it is sufficient only to pay consideration to variation of the initial threshold voltages of the transistors. Thus it is considered that, for example, around 0.2 V is sufficient.
The voltage application procedure shown in
By executing this procedure, if memory cells to which data has already been written and memory cells which are in their initial state are mixed together, individually for those memory cells which are in their initial states, or by executing this procedure all at once for a memory array of which all of the memory cells are in their initial state, it is possible to determine the data of those memory cells as “1” or “0”. In the following explanation, the procedure will be shown for forcibly determining the storage contents of a memory cell in its initial state to “1”.
Under the condition that the word line WL and the bit lines BLT and BLB are set to 0 V, first at the time instant T0 the source potential SL is raised from 0 V to Vcc and MCN1 and MCN2 are turned OFF, and then at the time instant T1, by dropping the pre-charge control signals PREB and PRET and the source potential VPST of the pre-charge transistor MP3 from Vcc to 0 V, the node B is charged up to Vcc by the pre-charge transistor MP4, and the node T is electrically discharged via the pre-charge transistor MP3. And, at the time instant T2, PREB and PRET return to Vcc, and then, at the time instant T3, by setting SL from Vcc to 0 V, due to the transistor MCN1 whose gate potential is the higher going to ON before the transistor MCN2, the node T is pulled down to 0 V in the state in which the node B is held at Vcc, so that the data in this flip-flop is determined as being “1”. And then, at the time instant T4, VPST is returned to Vcc.
The procedure shown in
By executing the procedure of
If this non-volatile memory cell is used instead of a fuse, and if its storage contents are uniquely determined to “1”, then, still in the initial state, it is possible to implement the state before cutting the fuse (corresponding to the data “1”).
While the data determination procedure shown in
The procedure shown in
And the procedure shown in
To compare this determination procedure with the determination procedure shown in
Moreover, the procedure shown in
With this eight transistor VPS divided type non-volatile memory cell of the second embodiment, in the state in which writing has not been performed, in other words in the state in which the threshold voltages of the storage transistors MCN1 and MCN2 are both low, the data cannot be determined by performing the raising processing (i.e. the data determination processing) shown in
The non-volatile memory cell shown in
When the power supply to the memory cell having this structure is turned ON in the state in which neither one of the storage transistors MCN1 and MCN2 has been written, the potential at the node T rises faster than that at the node B, and the load transistor MP1 and the storage transistor MCN2 go into the ON state, while the load transistor MP2 and the storage transistor MCN1 go into the OFF state; in other words, the data stabilizes at “0”.
It should be understood that, instead of unbalancing the channel widths as described above, it would also be acceptable to unbalance the channel lengths. Furthermore, it would also be acceptable for the load transistor whose channel width or channel length is changed to be either MP1 or MP2. Moreover, it would also be acceptable to perform this unbalancing by changing the channel width or the channel length of one of the storage transistors MCN1 or MCN2.
On the other hand, the non-volatile memory cell shown in
Due to this, when the power supply is turned ON in the state in which neither writing nor erasure of either of the two storage transistors MCN1 and MCN2 has been performed, since the potential of the node T rises quickly directly after the power supply has been turned ON while the potential of the node B rises more slowly, accordingly the system stabilizes with the load transistor MP1 and the storage transistor MCN2 in the ON state and the load transistor MP2 and the storage transistor MCN1 in the OFF state, in other words at the data “0”.
Although, in the example shown in
—The Threshold Voltage Measurement Method in the Second Embodiment—
It should be understood that, with this non-volatile memory cell of an eight transistor structure, it is possible to measure the threshold voltages of the storage transistors by establishing a potential arrangement as, for example, shown in
In
Since the gate potential of the load transistor MP2 (i.e. the node T) is set to 0.5 V, accordingly this transistor is turned ON if the potential of VPSB is greater than or equal to 0.5 V+Vthp, and potential comes to be supplied to the node B. On the other hand, since the gate potential PREB of the load transistor MP4 is set to 0 V, accordingly this transistor is turned ON if the potential of VPSB is greater than or equal to Vthp, so that it becomes possible for potential to be supplied to the node B. Vthp is the threshold voltage of the P-type MOS transistors shown by MP1 through MP4, and is around 0.7 V with a standard CMOS process, and it becomes possible to decide upon the threshold voltage of the transistor MCN1 (the gate voltage which is necessary for some fixed electrical current to flow) in a voltage range greater than or equal to this. When measuring the threshold voltage on the side of the transistor MCN1, the gate potential of the transistor MCN2 (the node T) is set to 0.5 V, in order for the gate potential of the transistor MCN1 (the node B) not to be pulled down by leakage electrical current on the side of the transistor MCN2.
While
It should be understood that although, in order to perform this threshold value measurement, the pre-charge line is divided into PRET and PREB, if this measurement is not to be performed, it would be acceptable to provide a single common pre-charge line both to the true side and to the bar side.
Embodiment ThreeA non-volatile storage device according to a third embodiment of the present invention, and a semiconductor integrated circuit device which incorporates it, will now be explained with reference to
The storage transistor side end portion of the true side inverter, in other words the source of the storage transistor MCN1, is connected to a true side source line SLT. Furthermore, the storage transistor side end portion of the bar side inverter, in other words the source of the storage transistor MCN2, is connected to a bar side source line SLB. And the load transistor side end portions of both of these inverters, in other words the sources of the load transistors MP1 and MP2, are connected to a line VPS.
In this flip-flop, the inverter in which the load transistor MP1 and the storage transistor MCN1 are connected in series functions as a storage unit on the true side, while the inverter in which the load transistor MP2 and the storage transistor MCN2 are connected in series functions as a storage unit on the bar side. The connection portion between the load transistor MP1 and the storage transistor MCN1 is a node T, while the connection portion between the load transistor MP2 and the storage transistor MCN2 is a node B. When the node T is at high potential and the node B is at low potential, the stored contents is “0”; while, when the node T is at low potential and the node B is at high potential, the stored contents is “1”.
The node T is connected to a bit line BLT (Bit Line-True) via a transfer gate MN1, while the node B is connected to a bit line BLB (Bit Line-Bar) via a transfer gate MN2. The transfer gates MN1 and MN2 are N-type MOS transistors, and a common word line WL is connected to both of these gates.
Furthermore a P-type MOS transistor MP3, which is a transistor for pre-charge, is connected in parallel with the load transistor MP1, in other words between the node T and VPS. Moreover a P-type MOS transistor MP4, which also is a transistor for pre-charge, is connected in parallel with the load transistor MP2, in other words between the node B and VPS. A T-side pre-charge line PRET is connected to the gate of the P-type MOS transistor MP3, while a B-side pre-charge line PREB is connected to the gate of the P-type MOS transistor MP4. Furthermore, all of the P-type MOS transistors MP1 through MP4 are formed within the same N well, and the potential of this N well is controlled by a signal VPM.
In
This storage transistor is an N-channel type transistor, and comprises, on the surface region of the P-type well 104, a drain 109 and a source 115 which are formed adjacent to the trenches 102 on the two sides, and a drain extension 107 which is formed in a region adjacent to the drain 109. The drain 109 and the source 115 are formed with an average arsenic density of 1·1020 cm−3, and the drain extension 107 is formed with an average arsenic density of 5·1018 cm−3.
Furthermore, upon the substrate in the channel region, which is the region of the surface of the P-type well 104 between the drain 109 and the source 115, there are formed a gate oxide layer 105 of thickness 5 nm, and a gate electrode 106 which is made from a polysilicon layer of thickness 200 nm and having a phosphorus density of 2·1020 cm−3. Furthermore, on both sides of this gate oxide layer 105 and gate electrode 106, there are formed side spacers 108 which are made as insulating layers of thickness 50 nm. It should be understood that the side spacer 108S on the source side is exposed to the channel region of the substrate, since no extension region is formed around the periphery of the source 115.
Furthermore, within the region of the P-type well 104, a P-type diffusion layer 111 having an average boron density of 1·1020 cm−3, which is an electrode for grounding this P-type well, is formed in a region which is separated from the storage transistor described above by one of the trenches 102.
With this storage transistor, the threshold voltage can be elevated by injecting carriers into the side spacer 108S on the source side. Furthermore, as will be explained with reference to
It should be understood that, although the initial threshold voltage of this storage transistor is 1.2 V, the variation is great since it is a transistor of a distinctive structure, and accordingly, from the point of view of reliability, it is not possible to utilize such a storage transistor singly as a storage element. Because of this, in this embodiment, the memory cell is built with the flip-flop structure shown in
In
In order to bring the storage transistor MCN1 to this potential configuration, voltages are applied to the memory cell in the condition shown in
Furthermore, when writing the data “1”, while the threshold voltage on the side of the storage transistor MCN2 becomes elevated, the other conditions are the same as when writing the data “0”, with only the voltage settings for BLT=Vcc and BLB=0 V being reversed.
It should be understood that although, in the embodiment described above, 6V was applied to the gate of the transistor MCN1 (the node B), and 6V was also applied to the source of the transistor MCN1 (the source line SL), it would also be acceptable for these voltages to be different voltages.
In the actual memory cell, these voltages are applied under the conditions shown in
Since, in this manner, with the voltage application conditions during writing as shown in
And
When the erase operation explained with reference to
Since, in this manner, the structure is arranged so that, even though the threshold voltages of the storage transistors MCN1 and MCN2 have once been raised, it is still possible again to lower them to the initial state Vth0, and furthermore since it is possible forcibly to determine the storage transistors MCN1 and MCN2 to the data “1”, even if they are both in the initial state Vth0, accordingly, even though requests for rewriting of the data have been issued a number of times, it is still possible to obtain a sufficient margin for reading out, which is the difference between the threshold voltages on the true side (the storage transistor MCN1) and on the bar side (the storage transistor MCN2).
By the writing operation shown in
The procedure shown in
At the time instant T2, PRET and PREB return to Vcc, and, from the time instant T3, the true side source potential SLT slowly drops towards 0 V. Moreover, at a time instant T4 which is more delayed than the time instant T3, the bar side source potential SLB slowly drops towards 0 V. At this time, control is performed so that SLB−SLT=ΔVs (for example ΔVs=0.2 V). Due to this, the voltage between the source and the drain of the storage transistor MCN2 comes to be controlled to be just ΔVs higher than the voltage between the source and the drain of the storage transistor MCN1, and thereby it is possible to make the apparent threshold voltage on the side of the storage transistor MCN2 higher by just the amount ΔVs.
At this time, if the storage contents of the memory cell is “1”, then, since the transistor MCN1 whose threshold voltage is the lower goes to ON before the transistor MCN2, accordingly the node T is pulled down to 0 V first while the node B goes to Vcc, so that the data of the flip-flop is determined at “1”. On the other hand, if the storage contents of the memory cell is “0”, then, since likewise the threshold voltage of the transistor MCN2 is lower than the threshold voltage of the transistor MCN1 (even though its threshold voltage is elevated by just the amount ΔVs) so that the storage transistor MCN2 goes to ON first, accordingly the node B is pulled down to 0 V first while the node T goes to Vcc, so that the data of the flip-flop is determined at “0”.
Furthermore, if the storage contents of the memory cell is “indeterminate”, in other words if the threshold voltages of both the transistors MCN1 and MCN2 are Vth0, then, since the apparent threshold voltage of the storage transistor MCN1 is just ΔVs lower than the threshold voltage of the storage transistor MCN2, accordingly the transistor MCN1 goes ON before the transistor MCN2, and the node T is pulled down to 0 V first while the node B goes to Vcc, so that the data of the flip-flop is determined at “1”.
Since often a memory cell in which the threshold voltages of MCN1 and MCN2 are both Vth0 is a cell to which, up till now, neither writing nor rewriting has been performed, and since, with this type of memory cell, the transistors do not deteriorate along with rewriting, accordingly, with regard to the setting of ΔV, it is sufficient only to pay consideration to variation of the initial threshold voltages of the transistors. Thus it is considered that, for example, around 0.2 V is sufficient.
The voltage application procedure shown in
By executing this procedure, if memory cells to which data has already been written and memory cells which are in their initial state are mixed together, individually for those memory cells which are in their initial states, or by executing this procedure all at once for a memory array of which all of the memory cells are in their initial state, it is possible to determine the data of those memory cells as “1” or “0”. In the following explanation, the procedure will be shown for forcibly determining the storage contents of a memory cell in its initial state to “1”.
Under the condition that the word line WL and the bit lines BLT and BLB are set to 0 V, and that VPS and VPM are set to Vcc, first at the time instant T0 the source potential SLB on the bar side is raised from 0 V to Vcc and the storage transistor MCN2 is turned OFF. Then, at the time instant T1, by dropping the pre-charge control signal PREB from Vcc to 0 V, the node B is charged up to Vcc by the pre-charge transistor MP4. At the time instant T2 PREB returns to Vcc, and then, at the time instant T3, SLB is returned from Vcc to 0 V. Due to this, by the transistor MCN1 whose gate potential is the higher going to ON before the transistor MCN2, in the state in which the node B is held at Vcc, the node T is pulled down to 0 V, so that the data in this flip-flop is determined as being “1”.
The procedure shown in
By executing the procedure of
If this non-volatile memory cell is used instead of a fuse, and if its storage contents are uniquely determined to “1”, then, still in the initial state, it is possible to implement the state before cutting the fuse (corresponding to the data “1”).
While the data determination procedure shown in
The procedure shown in
And the procedure shown in
To compare this determination procedure with the determination procedure shown in
Moreover, the procedure shown in
With this eight transistor SL divided type non-volatile memory cell of the third embodiment, in the state in which writing has not been performed, in other words in the state in is which the threshold voltages of the storage transistors MCN1 and MCN2 are both low, the data cannot be determined by performing the raising processing (i.e. the data determination processing) shown in
The non-volatile memory cell shown in
When the power supply to the memory cell having this structure is turned ON in the state in which neither one of the storage transistors MCN1 and MCN2 has been written, the potential at the node T rises faster than that at the node B, and the load transistor MP1 and the storage transistor MCN2 go into the ON state, while the load transistor MP2 and the storage transistor MCN1 go into the OFF state; in other words, the data stabilizes at “0”.
It should be understood that, instead of unbalancing the channel widths as described above, it would also be acceptable to unbalance the channel lengths. Furthermore, it would also be acceptable for the load transistor whose channel width or channel length is changed to be either MP1 or MP2. Moreover, it would also be acceptable to perform this unbalancing by changing the channel width or the channel length of one of the storage transistors MCN1 or MCN2.
On the other hand, the non-volatile memory cell shown in
Due to this, when the power supply is turned ON in the state in which neither writing nor erasure of either of the two storage transistors MCN1 and MCN2 has been performed, since the potential of the node T rises quickly directly after the power supply has been turned ON while the potential of the node B rises more slowly, accordingly the system stabilizes with the load transistor MP1 and the storage transistor MCN2 in the ON state and the load transistor MP2 and the storage transistor MCN1 in the OFF state, in other words at the data “0”.
Although, in the example shown in
—The Threshold Voltage Measurement Method in the Third Embodiment—
It should be understood that, with this non-volatile memory cell of an eight transistor structure, it is possible to measure the threshold voltages of the storage transistors by establishing a potential arrangement as, for example, shown in
In
Since the gate potential of the load transistor MP2 (i.e. the node T) is set to 1 V, accordingly this transistor is turned ON if the potential of VPSB is greater than or equal to 1 V+Vthp, and potential comes to be supplied to the node B. On the other hand, since the gate potential PREB of the load transistor MP4 is set to 0 V, accordingly this transistor is turned ON if the potential of VPSB is greater than or equal to Vthp, so that it becomes possible for potential to be supplied to the node B. Vthp is the threshold voltage of the P-type MOS transistors shown by MP1 through MP4, and is around 0.7 V with a standard CMOS process. Accordingly, it becomes possible to decide upon the threshold voltage of the transistor MCN1 (the gate voltage which is necessary for some fixed electrical current to flow) in a voltage range greater than or equal to this. When measuring the threshold voltage on the side of the transistor MCN1, the source potential of the transistor MCN2 and the MAP voltage and the bit lines are set to floating, in order to eliminate unnecessary leak-pass on the side of the transistor MCN2.
While
It should be understood that although, in order to perform this threshold value measurement, the pre-charge line is divided into PRET and PREB, if this measurement is not to be performed, it would be acceptable to provide a single common pre-charge line both to the true side and to the bar side.
—The Layout of the Second and Third Embodiments Upon the Semiconductor Substrate—
(A) of this figure shows the layout of the active regions and the gate electrodes upon the surface of the substrate. And (B) of this figure shows the second and third layers of metal wiring. As shown in (A) of this figure, the storage transistors on the true side and on the bar side are laid out in the same direction, so that it is arranged for the characteristics still to be mutually the same, even if an error occurs due to an impurity intruding diagonally.
Furthermore, as shown in (C) of this figure, the VPS lines and the source lines (SL) are divided, in this layout, into lines on the true side and lines on the bar side, so that, by shorting together either pair of these (making them common), it is possible to build a structure of the VPS divided type as in the second embodiment, or a structure of the SL divided type as in the third embodiment. In this manner, by employing the layout of this figure, while keeping the processing as far as the second layer of metal wiring the same, it is possible to manufacture either a non-volatile semiconductor memory cell of the VPS divided type of the second embodiment, or a non-volatile semiconductor memory cell of the SL divided type of the third embodiment, simply by changing only the third layer of metal wiring.
Embodiments Four and FiveIn the module EEPROM of the non-volatile storage device which is mounted to this RFID chip, there are written an ID number for authenticating the chip, an address for delivery service, goods information which is an alternative to a bar code (price, day of production, place of production, producer, component information, and so on), information required for an air cargo tag (name of carrier, name of owner, place of loading, destination, and so on), or the like.
In the interior of the level shift circuit 123, there are provided a static random access memory (SRAM) 124, a central processing device (CPU) 125, a cache memory (CACH) 126, a logic circuit (LOGIC) 127, a phase locked loop circuit (PLL) 128, an analog-digital conversion circuit (ADC) 129, a digital-analog conversion circuit (DAC) 130, and a system controller (SYSC) 131. Each of the units designated as 132, 133, and 134 is an electrically erasable and writable non-volatile memory (EEPROM), and is a non-volatile storage device according to the present invention having an appropriate predetermined capacity.
The non-volatile memory 132 is used for storing repair information for the SRAM 124 (i.e. control information for replacing defective memory cells with redundant memory cells). In other words, this semiconductor integrated circuit device includes circuits which may require repair (memory cells within the SRAM 124, if they become defective) and redundancy circuits (redundant memory cells within the SRAM 124) which can serve as alternatives to those circuits which may require repair; and, moreover, includes the non-volatile memory 132 which stores repair information. This repair information is information which specifies which circuits requiring repair may be replaced by which redundancy circuits.
Moreover, this semiconductor integrated circuit device includes an analog circuit and a constant trimming circuit which adjusts one or more circuit constants of this analog circuit. In this structure, the non-volatile memory 133 is used for storing information in this constant trimming circuit for specifying these circuit constants. Furthermore, this semiconductor integrated circuit device includes an oscillation circuit and a frequency trimming circuit which adjusts the oscillation frequency of the oscillation circuit. In this structure, the non-volatile memory 133 is used for storing information within this frequency trimming circuit for specifying this oscillation frequency. Yet further, this semiconductor integrated circuit device includes a reference voltage generation circuit and a voltage trimming circuit which adjusts the reference voltage generated by the reference voltage generation circuit. In this structure, the non-volatile memory 133 is used for storing information within this voltage trimming circuit for specifying this reference voltage. Even further, this semiconductor integrated circuit device includes a security circuit for identifying the chip. In this structure, the non-volatile memory 133 is used for storing information within this security circuit for identifying the chip.
Finally, the non-volatile memory 134 is endowed with 256 bits of memory capacity, and is used for storing ID information for this chip, operational mode information for this chip, and other appropriate data.
Claims
1. A non-volatile semiconductor storage device, comprising:
- a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected;
- two gate transistors, each respectively connected to a node of said flip-flop on a side thereof;
- two bit lines, each of which is connected to a respective one of said two gate transistors, and which are controlled to a voltage between operating power supply voltage and ground voltage;
- a word line which is connected to both of the gate electrodes of said two gate transistors, and which is controlled to a voltage between operating power supply voltage and ground voltage;
- a first voltage supply line which is connected to the sources of said storage transistors of said inverters, and to which a predetermined first voltage is supplied during writing and during erasure; and
- a second voltage supply line which is connected to the sources of said load transistors of said inverters, and to which a predetermined second voltage is supplied during writing; wherein said storage transistors of said inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates.
2. A non-volatile semiconductor storage device according to claim 1, wherein each of said storage transistor comprises:
- an insulation layer side spacer which is formed at a side portion of its gate electrode; and
- a low impurity density region which is formed at a border portion of its drain; and wherein:
- during writing, said first voltage supply line applies said first voltage to the sources of said storage transistors, and said second voltage supply line applies said second voltage to the gates of said storage transistors via the sources of said load transistors; and thereby information is written into said storage transistors by channel hot electrons being injected into said insulation layer side spacers; and
- during erasure, said first voltage supply line applies said first voltage to the sources of said storage transistors; and thereby information which is stored in said storage transistors is erased by an avalanche of hot holes being injected into said insulation layer side spacers.
3. A non-volatile semiconductor storage device according to claim 1, wherein each said inverter comprises a transistor for pre-charge which is connected in parallel with said load transistor thereof; and
- further comprising pre-charge control voltage supply lines which supply pre-charge control voltages to the gates of said transistors for pre-charge; and
- wherein said transistors for pre-charge are ON/OFF controlled independently from said load transistors by said pre-charge control voltages supplied by said pre-charge control voltage supply lines.
4. A non-volatile semiconductor storage device according to claim 3, wherein said second voltage supply line is provided separately for each of said inverters.
5. A non-volatile semiconductor storage device according to claim 3, wherein said first voltage supply line is provided separately for each of said inverters.
6. A non-volatile semiconductor storage device according to claim 1, wherein the continuity resistances of the load transistors of said two inverters are unbalanced.
7. A non-volatile semiconductor storage device according to claim 1, wherein the electrostatic capacitances with respect to the power supply voltage lines, or with respect to ground, of said two inverters are unbalanced.
8. A non-volatile semiconductor storage device according to claim 1, wherein the continuity resistances of the storage transistors of said two inverters are unbalanced.
9. A method for determining the state of a non-volatile semiconductor storage device according to claim 3, comprising a step of supplying a pre-charge control voltage selectively to one only of said pre-charge control voltage supply lines, and thereby turning only one but not the other of said transistors for pre-charge of said two inverters ON, thus forcibly determining the state of said flip-flop.
10. A method for determining the state of a non-volatile semiconductor storage device according to claim 4, comprising:
- a step of supplying a voltage lower than said first voltage to said first voltage supply line, and thereby raising the source potentials of said storage transistors of said two inverters and turning said storage transistors OFF;
- a step of supplying different voltages to said second voltage supply lines, thereby applying pre-charge voltages of different potentials to said nodes via said transistors for pre-charge of said two inverters; and
- a step of gradually decreasing said low voltage supplied to said first voltage supply line, thereby gradually lowering the source potentials of said storage transistors of said two inverters.
11. A method for determining the state of a non-volatile semiconductor storage device according to claim 4, comprising:
- a step of supplying voltages lower than said first voltage to said first voltage supply lines, and thereby raising the source potentials of said storage transistors of said two inverters and turning said storage transistors OFF;
- a step of supplying the same voltage to said second voltage supply lines, thereby applying pre-charge voltages of the same potential to said nodes via said transistors for pre-charge of said two inverters; and
- a step of gradually decreasing said low voltages supplied to said first voltage supply lines while maintaining a predetermined potential difference therebetween, thereby gradually lowering the source potentials of said storage transistors of said two inverters while maintaining a predetermined potential difference therebetween.
12. A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in claim 1, a circuit which may require repair comprising a portion which may require repair, and a redundancy circuit which serves as an alternative to said circuit which may require repair; and
- wherein said non-volatile semiconductor storage device is a storage circuit which stores repair information specifying which circuit may require repair by said redundancy circuit serving as an alternative thereto.
13. A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in claim 1, an analog circuit, and a constant trimming circuit which adjusts a circuit constant of said analog circuit; and
- wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said constant trimming circuit for specifying said circuit constant.
14. A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in claim 1, an oscillation circuit, and a frequency trimming circuit which adjusts the oscillation frequency of said oscillation circuit;
- and wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said frequency trimming circuit for specifying said oscillation frequency.
15. A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in claim 1, a reference voltage generation circuit, and a voltage trimming circuit which adjusts the reference voltage generated by said reference voltage generation circuit;
- and wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said voltage trimming circuit for specifying said reference voltage.
16. A semiconductor integrated circuit device comprising a non-volatile semiconductor storage device as described in claim 1, and a security circuit which identifies a chip in which said semiconductor integrated circuit device is mounted; and
- wherein said non-volatile semiconductor storage device is a storage circuit which stores information in said security circuit for specifying said chip.
Type: Application
Filed: Jun 5, 2007
Publication Date: Jan 24, 2008
Inventors: Taku OGURA (Amagasaki-shi), Masaaki Mihara (Amagasaki-shi), Yoshiki Kawajiri (Amagasaki-shi)
Application Number: 11/758,108
International Classification: G11C 5/06 (20060101);