Abstract: A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.

Abstract: A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit.

Abstract: A microprocessor which realizes fast register saving and restoring which are involved in subroutine calls, and is capable of reducing the scale of a program. A register file is provided with at least one register for storing data to be used for computational processing. A saving memory stores therein data saved from the registers. A saving control unit saves data from a writing destination register to the saving memory when an instruction to write to the register is executed in a subroutine. Then the saving control unit restores data saved in the saving memory back to the original registers when an instruction to return from the subroutine is executed.

Abstract: A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.

Abstract: A branch prediction method executed in a branch prediction circuit executes the branch instruction, the branch prediction method includes: a branch information storing process for storing the information in the first storage unit or the second storage unit; a process for determining on the basis of a branch condition set by the branch instruction and a realized branch whether the branch prediction is realized; a rewriting process for performing a rewrite of the information in one of the first storage unit and the second storage unit in accordance with the determination and the degree of likelihood that a branch indicated by the branch prediction occurs; and a process for performing branch prediction in response to the branch information when the branch instruction is executed in the processor.

Abstract: A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit.

Abstract: A cache memory system including a processing unit and a cache memory which is connected to the processing unit, wherein when a store instruction of storing write data into a certain address is executed, the cache memory system executes selectively one of, a first operation mode of allocating an area of the address to the cache memory in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data, and a second operation mode in response to a generation of a cache miss due to the access to the address and storing the write data to the cache memory without copying data of the address of the main memory unit to the allocated area on the cache memory.

Abstract: In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer 241. A branch prediction circuit 23 outputs hit information H/M as to whether or not an input address Ao is coincident with the branch instruction address, the valid bit which is also a branch prediction bit, the information POS, and the branch target address Apb. When a prediction error signal ERR is inactive, the address selection circuit 22 selectively outputs the output of an incrementer 21 and the branch target address Apb, based on the hit information H/M, the delay slot information POS, and the valid bit V.

Abstract: There is provided a processor including: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in the instruction pipeline or in an instruction prefetch buffer and an instruction code to be read next from an instruction cache memory or from a main memory, to judge whether or not the instruction codes are identical with each other; and a control unit whose control when the instruction codes are identical with each other is to read the instruction code neither from the instruction cache memory nor from the main memory but to process the instruction code stored in the instruction pipeline or in the instruction prefetch buffer again in the instruction pipeline or in the instruction prefetch buffer.

Abstract: A microprocessor which realizes fast register saving and restoring which are involved in subroutine calls, and is capable of reducing the scale of a program. A register file is provided with at least one register for storing data to be used for computational processing. A saving memory stores therein data saved from the registers. A saving control unit saves data from a writing destination register to the saving memory when an instruction to write to the register is executed in a subroutine. Then the saving control unit restores data saved in the saving memory back to the original registers when an instruction to return from the subroutine is executed.

Abstract: A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.

Abstract: A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract: A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.

Abstract: There is provided a processor including: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in the instruction pipeline or in an instruction prefetch buffer and an instruction code to be read next from an instruction cache memory or from a main memory, to judge whether or not the instruction codes are identical with each other; and a control unit whose control when the instruction codes are identical with each other is to read the instruction code neither from the instruction cache memory nor from the main memory but to process the instruction code stored in the instruction pipeline or in the instruction prefetch buffer again in the instruction pipeline or in the instruction prefetch buffer.

Abstract: A memory device that can handle various transmission-source devices and transmission-destination devices without modifying the hardware configuration. The memory device is used to transmit and receive data, and includes a data buffer for storing data output from a data-transmission source and outputting the data to a data-transmission destination serving as the data output destination; a transmission-source address converter for performing arrangement processing on the data output from the data-transmission source when the data-transmission source is a device that passively outputs data; and a transmission-destination address converter for performing arrangement processing on the data to be input to the data-transmission destination when the data-transmission destination is a device to which data is passively input.

Abstract: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Abstract: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target addre

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract: An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which generates a first index from an instruction address and the history stored in the history register, a history table which stores therein a portion of the instruction address as a tag and a first value indicative of likelihood of branching in association with the first index, a branch destination buffer which stores therein a branch destination address or predicted branch destination address of an instruction indicated by the instruction address and a second value indicative of likelihood of branching in association with a second index that is at least a portion of the instruction address, and a selection unit which makes a branch prediction by selecting one of the first value and the second value.