Abstract: In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer 241. A branch prediction circuit 23 outputs hit information H/M as to whether or not an input address Ao is coincident with the branch instruction address, the valid bit which is also a branch prediction bit, the information POS, and the branch target address Apb. When a prediction error signal ERR is inactive, the address selection circuit 22 selectively outputs the output of an incrementer 21 and the branch target address Apb, based on the hit information H/M, the delay slot information POS, and the valid bit V.

Abstract: An apparatus for branch prediction includes a history register which stores therein history of previous branch instructions, an index generation circuit which generates a first index from an instruction address and the history stored in the history register, a history table which stores therein a portion of the instruction address as a tag and a first value indicative of likelihood of branching in association with the first index, a branch destination buffer which stores therein a branch destination address or predicted branch destination address of an instruction indicated by the instruction address and a second value indicative of likelihood of branching in association with a second index that is at least a portion of the instruction address, and a selection unit which makes a branch prediction by selecting one of the first value and the second value.

Abstract: An information processing device for efficiently processing the VLIW instructions is disclosed. The information processing device includes an m×n (m-row×n-column) instruction buffer, a plurality of instruction executing parts executing a plurality of instructions in parallel, and a control circuit for selecting a predetermined number of instructions from the m×n instruction buffer and distributing the instructions to the instruction executing parts.

Abstract: A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.