Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract: A nonvolatile semiconductor memory unit which is provided with a nonvolatile semiconductor memory and a controller for performing a read operation, a write operation and an erase operation on the nonvolatile semiconductor memory unit, including an external power source which derives its supply of electric power from outside, an internal power source which derives its supply of electric power from a secondary battery and is connected to the nonvolatile semiconductor memory and the controller, a voltage detecting circuit for detecting a voltage of the external power source and a switching circuit which is provided between the external power source and the internal power source and is subjected to on-off control by an output of the voltage detecting circuit so as to enable and disable the external power source, respectively.

Abstract: A flash memory includes a user block for storage of user data, an alternate block reserved for substitution, a conversion table for storage of a physical address of the user block corresponding to a logical address, and an alternate table for storage of a physical address of the alternate block. A controller refers to the conversion table for writing the user data to a page within the user block. If the relevant page has data already written therein, the controller refers to the alternate table and writes the user data to a page within the alternate block to use it as a new user block, and switches the original user block to an alternate block. This permits rapid rewriting of the user data.

Abstract: A nonvolatile semiconductor memory unit which is provided with a nonvolatile semiconductor memory and a controller for performing a read operation, a write operation and an erase operation on the nonvolatile semiconductor memory unit, including an external power source which derives its supply of electric power from outside, an internal power source which derives its supply of electric power from a secondary battery and is connected to the nonvolatile semiconductor memory and the controller, a voltage detecting circuit for detecting a voltage of the external power source and a switching circuit which is provided between the external power source and the internal power source and is subjected to on-off control by an output of the voltage detecting circuit so as to enable and disable the external power source, respectively.

Abstract: A nonvolatile semiconductor storage device directly connected to CPU buses and general-purpose buses is provided. The device has a nonvolatile memory cell array with block units including a plurality of sectors. Each sector stores user data by being specified each address. The device has a sequencer which judges whether predetermined types of the access operation is carried out or not. The judgment is achieved based on: a command register which sets a command to specify type of access operation to the array; an address register which sets the access address; a count register which sets a number of the sectors to be accessed; a status register which holds status indicating whether processing according to the command set to the command register; status; and the command. The sequencer accesses to the array based on the address set and the number of sectors when the access operation is carried out.

Abstract: An external memory includes a RAM of a fixed size for storing firmware, and a flash memory group. Since the flash memory group is accessible on a block-by-block basis, a plurality of program codes each corresponding to one processing routine are individually accessible. The RAM includes a first storage region (91) serving as a dynamic load area to which a program code stored in each block of the flash memory group is exclusively loaded. The exclusive loading of the plurality of program codes each corresponding to the respective one processing routine to the first storage region allows a smaller required size of the RAM. Since the flash memory group is rewritable, the firmware may be subjected to modification and version update. In this case, the required size of the RAM is not increased. Therefore, the external memory can store the firmware of a size exceeding the fixed size of the RAM.

Abstract: A card, which is one of portable storage devices, fills its functions when connected to a terminal device. The card stores a random number table RND. The card calculates a function value f(RND[i]) of a preset function f by setting the argument of the function f as a random number RND[i] corresponding to the index number i which is designated from the random number table RND by the terminal device. Then the card compares and collates the functional value f(RND[i]) with a collating value G which is specially supplied by the terminal device. The card becomes a free state if the function value f(RND[i]) coincides with the collating value G, while it maintains the lock state if the function value f(RND[i]) does not coincide with the collating value G. Then the index number, which has been once used, is excluded in the following comparing or collating operations. In consequence, illegal access to the information stored in the card is surely prevented.

Abstract: There is provided a processing system capable of preventing third parties from improper operation. Referring to FIG. 4, a storage device generates a pseudo random number (key data k), calculates a value g (k) of a function g, rearranges each bit of the key data k and value g (k) in accordance with a predetermined method, transmits them to a terminal device, and calculates a value f (k) of a function f. The terminal device receives data and calculates a value g (k). The terminal device compares the value g (k) received from the storage device and the value g (k) calculated by the terminal device. If the values do not match, access to the storage device is stopped. If the values match, the terminal device calculates and transmits value f (k) to the storage device. The storage device compares the value f (k) calculated by the storage device and the value f (k) received from the terminal device and responds to a result of the comparison by determining whether to permit access from the terminal device.

Abstract: A capacity size of a single block of a flash memory (2) is an integer multiple of a single sector size which is a processing unit of an external host (4), and each of the first and second buffer RAMs interposed between the external host and the flash memory has a capacity corresponding to a single sector size of the flash memory, and data transmission between the external host and the buffer RAMs and between the flash memory and the buffer RAMs are performed by alternately selecting different buffer RAMs, and thus the data transmission between the buffer RAMs and the external host is performed simultaneously. and in parallel with performing the data transmission between the buffer RAMs and the flash memory.

Abstract: Nonvolatile semiconductor memory has simple user interface including defective sector management. Nonvolatile table memory stores an address conversion table for converting an externally applied logical sector address to a physical sector address. An address decoder outputs a specific selection signal corresponding to a physical sector address output from the table memory. The storage area of the memory matrix is divided into a plurality of sectors. The memory matrix interfaces with a data register for reading data loaded therein as necessary. The address conversion table of the table memory is read according to logical sector address input, and a physical sector address corresponding to the logical sector address is output to the address decoder.

Abstract: An object is to obtain a nonvolatile semiconductor memory device which can achieve a reduction in processing time required for data writing operation and an increase in storage density through the use of multi-valued MOS transistors. In operation for writing data into cells, the amount of charge injected into the floating gates is controlled so as to set the threshold voltages of the MOS transistors at all different values. When reading data from the cells, the data is read by determining whether the threshold voltages of the MOS transistors are higher or lower relative to each other.

Abstract: An IC memory card and an IC memory card system prevent the use of unauthorized or illegal copies or forgeries of IC memory cards storing original content. Using a key value selected by a terminal device of the IC memory card system, the terminal device calculates a first value and the IC memory card separately calculates a third value by applying a particular method to the key value. Second and fourth values are similarly calculated using a different particular method. The IC memory card then determines whether the first and third values are the same. The terminal device separately determines whether the second and fourth values are the same. Only if the first and third values are confirmed to match, and then the second and fourth values are also confirmed to match, does the terminal device recognize the IC memory card as an authentic IC memory card and not an unauthorized or illegal copy or forgery.

Abstract: A memory card includes an error-correction-code (ECC) controller for generating ECCs, an ECC memory for storing ECCs generated by the ECC controller and an address converter for converting between addresses of the ECC memory and those of a main memory for storing data. The ECC controller generates an ECC to be stored in the ECC memory when a control data is input and the address converter fetches a relationship between an address of the ECC memory at which the generated ECC is stored and that of the main memory at which the control data is stored. Upon reading data stored in the main memory, error check and error correction operations are executed for the control data.

Abstract: A memory card consisting of volatile memory that is used connected to a host system apparatus and operated by a power supplied from said host system apparatus, comprises a main memory consisting of volatile memory and a submemory consisting of flash memory wherein when the power is tuned off, the host system apparatus copies data stored in the main memory into the submemory at addresses, corresponding to addresses of the main memory, and when the power is turned on, the host system apparatus writes data stored in the submemory into the main memory at the original addresses.

Abstract: In a system wherein a memory card is connected to a computer, data stored in a memory device in the memory card is read by a processor provided in the computer. An address signal and a data signal from the computer to the memory card, and/or a data signal from the memory card to the computer are coded with coding keys by a coder, while the coded signal is decoded by a decoder with a decoding key corresponding to the coding keys. The coder and the decoder adopts a public key system, and it is difficult to determine the decoding key even if the coding keys are known. In modified examples, coding keys are not provided beforehand in the computer or memory card, and they are latched in a latch device when the memory card is connected to the computer. When the coding keys and decoding keys are stored in the memory card, they are changed for each memory card.

Abstract: The objective of the invention is to provide a portable information processing apparatus and a PC card for its expansion that facilitate transient and still images. A PC card system of the invention comprises a PC card capable of processing video signals and an information processing apparatus having a liquid crystal display, PC card slots, a VGA controller that converts pixel data into analog RGB signals, and an LCD controller that controls the liquid crystal display. The information processing apparatus further has an analog RGB signal lines and synchronizing signal lines between the LCD controller and the PC card slots, and a pixel data bus between the VGA controller and the PC card slots.

Abstract: The memory card of the present invention includes an error correction circuit having an error correction code (ECC) computing circuit for computing the error correction codes, in blocks, for the data stored in a main memory, an ECC memory for storing the error correction codes computed by the ECC computing circuit, an ECC control circuit for comparing error correction codes computed for updated data with error correction codes previously computed for corresponding original data stored in the ECC memory, and for producing a signal indicating the result of the comparison, and an error correction controller for finding and correcting errors based on the result of the comparison produced by the ECC control circuit.