Patents by Inventor Yoshimasa Yoshimura

Yoshimasa Yoshimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5802328
    Abstract: The PC card system device including a PC card in conformity with the PC card standard and an information processing device which the PC card is to be connected, comprises a card connector provided in the PC card, a device connector, provided in the information processing device, a connection state detector for detecting the connection state of the PC card according to the signal level of at least one contact of the device connector, and an interface controller for controlling the signal transfer from the device connector according to the determination of the connection state detector. The interface controller prohibits any signal transfer from the device connector if the connection state detector determines that the PC card is incorrectly connected to the information processing device.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: September 1, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshimasa Yoshimura
  • Patent number: 5650974
    Abstract: A semiconductor device includes a first battery BAT 1; a second battery BAT 2; and switches SW1, SW2, SW3, and SW4. Switching block 13 is provided for switching a power source for backing up a memory 3 to retain data. Also a voltage comparator 5 is provided for comparing an external power supply voltage supplied by the power supply VCC of a host apparatus with a reference voltage Vref. In response to the signal from a main battery presence sensor block for sensing the presence of the first battery BAT 1 and the signal from the voltage comparator 5, the memory 3 is backed up to retain data by the external power supply voltage when it is supplied, and further, the second battery BAT 2 is charged by a charging circuit 6 driven by the external power supply voltage. When neither external power supply voltage nor first battery BAT 1 is present, the second battery BAT 2 backs up the memory 3 to retain data.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: July 22, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshimasa Yoshimura
  • Patent number: 5629642
    Abstract: In a power supply monitor which outputs a reset signal when the power supply voltage decreases, a first voltage is generated by a first voltage generator in proportion to a power supply voltage, and a comparator supplying a first signal when the first voltage becomes lower than a reference voltage. On the other hand, a slewing rate detector supplies a second signal when a slewing rate of decreasing in power supply voltage is larger than a threshold value. Then, a signal generator supplying a signal set by a trailing edge of the second signal received from the slewing rate detector except a period after the second signal is received and reset by a trailing edge of the first signal received from the comparator. That is, even if the power supply voltage decreases, the monitor does not generate a reset signal when the decrease in the power supply voltage is instantaneous.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: May 13, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshimasa Yoshimura
  • Patent number: 5502682
    Abstract: A semiconductor integrated circuit for controlling a power source with which a power source potential on the basis of different external power source potentials, for example, 5 V and 3 V, can accurately be obtained. The semiconductor integrated circuit for switching between an external power source and a backup power source has an arrangement that, when the external power source potential is supplied to an external power source potential node, the potential at a first connection node on the basis of the external power source potential and a first reference potential of a first reference potential generating circuit are subjected to a comparison by a first comparator, and a first power source potential discriminating portion transmits a first comparison result signal.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: March 26, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshimasa Yoshimura
  • Patent number: 5394300
    Abstract: In an IC memory card, sub-modules, in each of which a plurality of memory ICs are mounted on each of two opposed surfaces of a sub-substrate, are mounted on each of two opposed surfaces of a single substrate. Since the number of substrates connected to a connector is one, soldering of the connector is facilitated, and the structure of the connector can be simplified. Furthermore, in an IC memory card, the sub-modules may be mounted on the substrate in such a manner that they are stacked in two stages at an opening in the substrate. In this way, the thickness of the IC memory card can be minimized. Also, the use of the die bonding process makes connection between the sub-module and the substrate easy.
    Type: Grant
    Filed: January 11, 1993
    Date of Patent: February 28, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshimasa Yoshimura