Abstract: Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit (3) includes a first switch circuit (22) provided between a pixel node Np of a display element unit (21) and a data signal line SL, and a memory circuit (23) which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm.

Abstract: A pixel circuit includes: a light emitting element; an n-channel drive transistor T1 that has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor T2 which is interposed between a data signal line and the pixel node, and has a gate connected with a scan signal line; a control transistor T3 which is interposed between the source and a drain of the drive transistor T1, has a gate connected with the scan signal line, and comes into an ON state simultaneously with the transfer transistor T2; and a capacitance element which is interposed between the gate and the source of the drive transistor T1, and holds the light emission control voltage.

Abstract: An organic EL display device includes a controller, a data driver, and a DRAM which provides a gain correction memory and a threshold voltage correction memory. The data driver sends, to the controller, first and second measurement data Im corresponding to the first and second measuring data voltages Vm, respectively. The controller compares ideal characteristic data IO(P) with the first and second measurement data Im, and updates threshold voltage correction data Vt and gain correction data B2R based on the comparison results. The controller corrects video data Vm based on the threshold voltage correction data Vt and the gain correction data B2R. Thereby, both threshold voltage compensation and gain compensation of a drive transistor are performed with respect to each pixel circuit, while display is performed.

Abstract: Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage.

Abstract: Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction.

Abstract: Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T1, a source of a second transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T1 and a drain of the second transistor element T2.

Abstract: An organic EL display device includes a controller, a data driver, and a DRAM which provides a gain correction memory and a threshold voltage correction memory. The data driver sends, to the controller, first and second measurement data Im corresponding to the first and second measuring data voltages Vm, respectively. The controller compares ideal characteristic data IO(P) with the first and second measurement data Im, and updates threshold voltage correction data Vt and gain correction data B2R based on the comparison results. The controller corrects video data Vm based on the threshold voltage correction data Vt and the gain correction data B2R. Thereby, both threshold voltage compensation and gain compensation of a drive transistor are performed with respect to each pixel circuit, while display is performed.

Abstract: Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction.

Abstract: Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T1, a source of a second transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T1 and a drain of the second transistor element T2.

Abstract: A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively.

Abstract: A display device includes liquid crystal capacitor element formed between a pixel electrode and a counter electrode. One terminals of the pixel electrode, a first switch circuit, and a second switch circuit, and a first terminal of a second transistor form an internal node. The first switch circuit and the second switch circuit have other terminals connected to a source line. The second switch circuit is configured by a series circuit of transistors, and a control terminal of the transistor, a second terminal of the transistor, and one terminal of a boost capacitor element form an output node. The other terminal of the boost capacitor element is connected to a boost line, the control terminal of the transistor is connected to a reference line, and the control terminal of the transistor is connected to a selecting line.

Abstract: Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit (3) includes a first switch circuit (22) provided between a pixel node Np of a display element unit (21) and a data signal line SL, and a memory circuit (23) which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm.

Abstract: Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage.

Abstract: A pixel circuit includes: a light emitting element; an n-channel drive transistor T1 that has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor T2 which is interposed between a data signal line and the pixel node, and has a gate connected with a scan signal line; a control transistor T3 which is interposed between the source and a drain of the drive transistor T1, has a gate connected with the scan signal line, and comes into an ON state simultaneously with the transfer transistor T2; and a capacitance element which is interposed between the gate and the source of the drive transistor T1, and holds the light emission control voltage.

Abstract: A display device which realizes a multi-gradation constant display with low power consumption is provided.

Abstract: In a display device including a pixel circuit having a transistor with a low electron mobility, low power consumption is realized without decreasing an aperture ratio. An liquid crystal capacitor element (Clc) is formed between a pixel circuit (20) and a counter electrode (80). One ends of the pixel electrode (20), a first switch circuit (22), and a second switch circuit (23) and a first terminal of a second transistor (T2) form an internal node (N1). The other end of the first switch circuit (22) is connected to a source line (SL). The second switch circuit (23) has the other end connected to a voltage supply line (VSL), and is a series circuit of transistors (T1 and T3). A control terminal of the transistor (T1), a second terminal of the transistor (T2), and one end of the boost capacitor element (Cbst) form an output node (N2). The other end of the boost capacitor element (Cbst) and the control terminal of the transistor (T2) are connected to a selecting line (SEL) and a reference line REF, respectively.

Abstract: A liquid crystal display device is provided which is capable of sufficiently decreasing power consumption in permanent display of still images while keeping high quality display in transparent mode, in high resolution display panels. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a reference voltage to the pixel electrode as a refreshing voltage. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.

Abstract: A display device which can prevent deterioration of a liquid crystal and reduction in display quality at low power consumption without lowering an aperture ratio is provided. An opposite voltage (Vcom) is applied to an opposite electrode (80) of a liquid crystal capacitive element (Clc). One ends of a pixel electrode (20), a first switch circuit (22), a second switch circuit (23), and a first terminal of a second transistor (T2) form an internal node (N1). The other ends of the first switch circuit (22) and the second switch circuit (23) are connected to a source line (SL) and a voltage supply line (VSL), respectively. A control terminal of a first transistor (T1) in the second switch circuit (23), a second terminal of the second transistor (T2), and one end of a boost capacitive element (Cbst) form an output node (N2). The other end of the boost capacitive element (Cbst) and the control terminal of the second transistor (T2) are connected to a boost line (BST) and a reference line (REF), respectively.

Abstract: A display device which realizes constant display having multiple tones with low power consumption is provided.

Abstract: In a display device, a liquid crystal capacitive element is sandwiched between a pixel electrode and an opposite electrode. The pixel electrode, one end of a first switch circuit, one end of a second switch circuit and a first terminal of a second transistor form an internal node. The other terminals of the first switch circuit and the second switch circuit are connected to a source line. The second switch circuit is a series circuit composed of a first transistor and a diode. A control terminal of the first transistor, a second terminal of the second transistor and one end of a boost capacitive element form an output node. The other end of the boost capacitive element and the control terminal of the second transistor are connected to a boost line and a reference line, respectively.