Abstract: There is provided a nonvolatile semiconductor storage device capable of securing sufficient read accuracy without providing superfluous sense time margin when there are variations in temperature and transistor characteristics. This nonvolatile semiconductor storage device includes a reference cell 2 whose threshold value is preparatorily set to a value between a lower limit of a threshold voltage distribution in a state 0 in which nonvolatile memory cells MC00 through MC12 have a high threshold value and an upper limit of a threshold voltage distribution in a state 1 in which the memory cells have a low threshold value. When the characteristics of the nonvolatile memory cells MC00 through MC12 shift due to the influence of a change in temperature or the like, the characteristics of the reference cell 2 shift so as to follow this characteristic shift.

Abstract: A cell array comprising nonvolatile memory cells having; a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction; wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction, the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another cell adjacent to said one cell in the X direction, the control gates of the cells arranged along the

Abstract: A nonvolatile semiconductor memory device comprises: a pair of impurity diffusion layers formed on a surface of a semiconductor substrate; two control gates formed on the semiconductor substrate through the intervention of a charge accumulating layer, the two control gates being provided between the pair of impurity diffusion layers and adjacent to each of the impurity diffusion layers; a word gate transistor including a word line formed on the semiconductor substrate through the intervention of a word gate insulating film between the control gates, wherein the two control gates and the word gate transistor are connected in series to form a unit cell.

Abstract: There is provided a nonvolatile semiconductor storage device capable of securing sufficient read accuracy without providing superfluous sense time margin when there are variations in temperature and transistor characteristics. This nonvolatile semiconductor storage device includes a reference cell 2 whose threshold value is preparatorily set to a value between a lower limit of a threshold voltage distribution in a state 0 in which nonvolatile memory cells MC00 through MC12 have a high threshold value and an upper limit of a threshold voltage distribution in a state 1 in which the memory cells have a low threshold value. When the characteristics of the nonvolatile memory cells MC00 through MC12 shift due to the influence of a change in temperature or the like, the characteristics of the reference cell 2 shift so as to follow this characteristic shift.

Abstract: A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.

Abstract: A cell array comprising a nonvolatile memory cells having; a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction; wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction, the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another cell adjacent to said one cell in the X direction, the control gates of the cells arranged along t

Abstract: A nonvolatile semiconductor memory including at least two cells each comprising: a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed on the semiconductor substrate with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in the channel direction, wherein the floating gate and the split gate of one cell are alternately arranged with the floating gate and the split gate of another adjacent cell along the channel direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another adjacent cell.

Abstract: The nonvolatile semiconductor memory of this invention includes: a semiconductor substrate; a plurality of memory cells formed in a matrix on the semiconductor substrate, each of the memory cells including a first insulating film formed on the semiconductor substrate, a floating gate formed on the first insulating film, and a control gate formed on the floating gate via a second insulating film sandwiched therebetween, a source diffusion region, and a drain diffusion region; a diffusion layer formed in a portion of the semiconductor substrate located between two of the memory cells adjacent in a first direction, the diffusion layer including the drain diffusion region for one of the two memory cells and the source diffusion region for the other memory cell; a word line formed by connecting the control gates of the memory cells lined in the first direction; and a bit line formed by connecting the diffusion layers lined in a second direction substantially perpendicular to the first direction, wherein the memory

Abstract: A non-volatile memory includes: at least one memory cell including one non-volatile memory transistor and one capacitor; the non-volatile memory transistor being composed of a first dielectric film, a floating gate, a second dielectric film and a control gate sequentially laminated on a semiconductor substrate, and source/drain diffusion layers formed in the semiconductor substrate; the capacitor being composed of a capacitor dielectric film sandwiched between two electrodes, one of the electrodes being connected to the source diffusion layer of the non-volatile memory transistor; and an injecting/drawing means for injecting/drawing electrons from the drain diffusion layer to the floating gate by use of a tunnel current.

Abstract: In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.

Abstract: The nonvolatile semiconductor memory of this invention includes: a semiconductor substrate; a plurality of memory cells formed in a matrix on the semiconductor substrate, each of the memory cells including a first insulating film formed on the semiconductor substrate, a floating gate formed on the first insulating film, and a control gate formed on the floating gate via a second insulating film sandwiched therebetween, a source diffusion region, and a drain diffusion region; a diffusion layer formed in a portion of the semiconductor substrate located between two of the memory cells adjacent in a first direction, the diffusion layer including the drain diffusion region for one of the two memory cells and the source diffusion region for the other memory cell; a word line formed by connecting the control gates of the memory cells lined in the first direction; and a bit line formed by connecting the diffusion layers lined in a second direction substantially perpendicular to the first direction, wherein the memory

Abstract: A semiconductor memory has a random access memory (DRAM) and a mask read only memory (MROM) formed on the same semiconductor substrate; each of the DRAM and MROM comprising a plurality of word lines, a plurality of bit lines and a plurality of memory cells: each of the memory cells included in the DRAM and the MROM comprising; a switching element including a source and drain regions and a gate electrode; a capacitance element formed of a lamination of an insulating film and a plate electrode subsequently laminated in this order; and a conductive parts connecting the switching element to the word lines, the bit lines, and a capacitance element; the MROM including a predetermined memory cell which lacks at least one part of the conductive parts.

Abstract: A method for manufacturing a non-volatile memory comprising the steps of:(i) forming a first electrode on a semiconductor substrate having a first insulating film;(ii) implanting impurity ions to an area adjacent to one side of the first electrode while masking at least an area adjacent to another side of the first electrode;(iii) forming a second insulating film on the semiconductor substrate including the first electrode, followed by depositing a conductive film on the entire surface of the second insulating film;(iv) implanting impurity ions into the semiconductor substrate via the conductive film; and(v) patterning the conductive film to constitute a second electrode.

Abstract: A non-volatile memory having a Floating Gate Oxide type field effect transistor provided with a floating gate on a semiconductor substrate through a tunnel oxide film, including an oxide blocking film formed on the side wall of the floating gate for preventing a tunnel insulating film from being thermally oxidized by thermal oxidation.

Abstract: A method for forming a semiconductor device comprising steps of: (i) depositing an oxide film and then an anti-oxide film on a semiconductor substrate of a first conductive type, (ii) removing the anti-oxide film provided in a prescribed region where a field oxide film is to be formed, followed by forming a resist on the semiconductor substrate including the anti-oxide film in a prescribed region where a buried bit line is to be formed, (iii) implanting ions of a second conductive type to the semiconductor substrate using the oxide film and the resist as a mask, (iv) forming the field oxide film in the prescribed region by LOCOS method, followed by forming a gate electrode on the semiconductor substrate, (v) implanting ions of the second conductive type to the semiconductor substrate using the gate electrode as a mask and subjecting the resulting semiconductor substrate to a thermal treatment, thereby forming a source/drain region to which the buried bit line is connected.

Abstract: A nonvolatile memory including a plurality of memory cells comprising a semiconductor substrate, a first electrode formed on the substrate, a floating gate formed on the side wall of the first electrode, and a second electrode, wherein the memory cells are arranged in X and Y directions to form a matrix; the first electrodes of memory cells arranged in the Y direction are connected in common in the Y direction, the second electrodes are connected in common in the Y direction; a memory cell and one of its adjacent memory cells arranged in the X direction have a first impurity diffused layer in common; the memory cell and the other adjacent memory thereof have a second impurity diffused layer in common; and the first impurity diffused layers of the memory cells arranged in the X direction are further connected in common by a conductive layer.

Abstract: A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjacent thereto, the tunnel regions of the respective EEPROMs being provided as self-aligned with the respective ends of the thermal oxide film and positioned at the respective ends of an impurity ion implantation pattern for use in forming a source region of the EEPROMs.

Abstract: A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them. The non-volatile memory further includes a programmable insulating film provided in self-alignment between the gate electrode and at least one of the source and drain diffusion layers and the programmable insulating film is broken down by a voltage applied to the gate electrode so as to execute programming.

Abstract: The present invention provides a nonvolatile memory and a method of writing data thereto. The nonvolatile memory includes a memory cell having a semiconductor substrate, a first electrode on the substrate formed through the intermediary of an insulating film, a floating gate adjacent to the first electrode formed through the intermediary of an insulating film, and a second electrode deposited at least on the floating gate through the intermediary of an insulating film, wherein a plurality of the memory cells are arranged in the directions of X and Y to form a matrix, at least 2 memory cells arranged in the direction of X form a memory cell group, a single first impurity diffused layer and a single second impurity diffused layer used in common in the respective cells are formed at the both ends of the memory cell group, and the first electrode and the second electrode of the plurality of memory cells arranged in the direction of Y are connected in common.

Abstract: The nonvolatile semiconductor memory of this invention includes: a semiconductor substrate; a plurality of memory cells formed in a matrix on the semiconductor substrate, each of the memory cells including a first insulating film formed on the semiconductor substrate, a floating gate formed on the first insulating film, and a control gate formed on the floating gate via a second insulating film sandwiched therebetween, a source diffusion region, and a drain diffusion region; a diffusion layer formed in a portion of the semiconductor substrate located between two of the memory cells adjacent in a first direction, the diffusion layer including the drain diffusion region for one of the two memory cells and the source diffusion region for the other memory cell; a word line formed by connecting the control gates of the memory cells lined in the first direction; and a bit line formed by connecting the diffusion layers lined in a second direction substantially perpendicular to the first direction, wherein the memory