Abstract: A non-volatile memory having a memory cell, the memory cell including a semiconductor substrate having first and second impurity diffusion layers, a first insulating film provided on the semiconductor substrate between the first and second impurity diffusion layers and on the first impurity diffusion layer side, a tunnel dielectric film extended to a second impurity diffusion layer region which is provided opposite to the first impurity diffusion layer side, a first electrode formed on the first insulating film, a floating gate formed on the tunnel dielectric film and on the side wall of the first electrode through an insulating film, and a second electrode provided at least on the floating gate through a second insulating film so as to control the potential of the floating gate, wherein channel hot electrons can be injected from the inversion layer formed under the first electrode, which is controlled by the first electrode, to the floating gate.

Abstract: A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown strength on the source side than on the drain side, wherein the insulating film is comprised of a laminated film having a multilayer structure on the drain side and a single-layer film or multilayer film which is broken down at a smaller voltage on the source side than on the drain side, and a predetermined voltage is applied to break down the single-layer film or multilayer film on the source side, so that data can electrically be written only once.

Abstract: A semiconductor memory comprises a plurality of non-volatile DRAMs and volatile DRAMs overlaying an identical semiconductor substrate, each of the non-volatile DRAMs comprising a word select transistor having a word selective gate electrode, a recall transistor having a recall gate electrode, a Flotox type memory transistor having a floating gate electrode and a capacitor having a storage node and a capacitor electrode, and each of the volatile DRAMs comprising a select transistor having a selective gate electrode and a capacitor having a capacitor lower electrode, a storage node and a capacitor upper electrode; the word selective gate electrode, the recall gate electrode and the floating gate electrode in the non-volatile DRAM and the selective gate electrode and the capacitor lower electrode in the volatile DRAM being formed of a first conductive layer on the semiconductor substrate, the storage nodes in the non-volatile DRAM and volatile DRAM being formed of a second conductive layer on the first conductiv

Abstract: This invention is directed to a process for the fabrication of a stacked semiconductor nonvolatile memory device, which process is adapted to define a longitudinal length of a floating gate in self-alignment with overlying control gate and interlayer insulating film by etching, without severely damaging the underlying semiconductor substrate.

Abstract: A semiconductor memory includes a transistor and a capacitor which are formed on a semiconductor substrate, wherein the capacitor comprises in superposed layers a first capacitor composed of an impurity diffused layer formed in a surface layer of the semiconductor substrate, a first dielectric formed on the impurity diffused layer and a lower plate electrode formed on the first dielectric and serving as a field plate; a second capacitor composed of the lower plate electrode, a second dielectric formed on the lower plate electrode and a node electrode formed on the second dielectric; and a third capacitor composed of the node electrode, a third dielectric formed on the node electrode and an upper plate electrode formed on the third dielectric.

Abstract: A non-volatile memory comprises an auxiliary gate of polysilicon provided on a Si substrate having a gate insulating film and a field oxidation film; a floating gate which is provided on a side wall of the auxiliary gate lying in an active region with a small piece of a first insulating film interposed between them and which is formed by etchback of useless part of a polysilicon side wall spacer; and a control gate of polysilicon provided at least on the floating gate including a second insulating film interposed between them; the floating gate being formed in self-alignment to the control gate.

Abstract: A semiconductor memory device has memory cells where each cell is constructed with a volatile memory and a non-volatile memory. The semiconductor memory device has a non-volatile memory initializing mode in which the data in the non-volatile memory is erased and a temporary latch by a sense amplifier of data in the volatile memory is done during the nonvolatile memory initializing mode. Initialization of the non-volatile memory is achieved by injecting electrons into the non-volatile memory. If sufficient electrons are present in the non-volatile memory when the non-volatile memory initializing mode is required, it is not necessary to inject electrons. After the non-volatile memory is initialized, new data is written to the non-volatile memory via the volatile memory by injecting holes into the non-volatile memory in an EEPROM mode.

Abstract: A method which can operate a semiconductor memory device having a volatile memory and a non-volatile memory without lowering the retention characteristic of the non-volatile memory is described. The volatile memory includes a MOS transistor, and a capacitor, one electrode of which is connected to the source of the MOS transistor. The non-volatile memory includes a floating gate transistor. The semiconductor memory device further has a switch connected between the source of the MOS transistor and the drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. When the switch is off and the volatile memory to be operated, a voltage which is substantially one half of that of a power source voltage with respect to the ground level is applied to the source of the floating gate transistor.

Abstract: A semiconductor memory device having memory cells in which a DRAM section and an EEPROM section are combined, and a transistor for transferring data between the DRAM and EEPROM sections is disclosed. The DRAM section includes a MOS transistor, and a capacitor one electrode of which is connected to the source of the MOS transistor. The EEPROM section has a floating gate transistor. The transistor for transfer is connected between the source of the MOS transistor and the source/drain of the floating gate transistor. The control gate of the floating gate transistor is connected to the source of the MOS transistor. Methods of rewriting and recalling data in the semiconductor memory device are also disclosed. The methods can be performed without shortening the life of the EEPROM section.

Abstract: A nonvolatile semiconductor memory device including a semiconductor substrate, a pair of impurity diffusion regions provided in the substrate, a gate region provided between the pair of impurity diffusion regions, a first gate electrode stacked on the gate region via a first dielectric film, and a second gate electrode stacked on the first gate electrode via a second dielectric film, the first gate electrode being electrically short-circuited to one of the impurity diffusion regions.

Abstract: A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch circuit for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated. The EEPROM consists of a floating gate and a control gate, and the mode switch circuit consists of a MOS transistor having a control gate integrally formed with the control gate of the EEPROM.

Abstract: An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:(a) forming on a silicon substrate a silicon nitride layer having a predetermined pattern and a tapered-slant side wall, between the silicon nitride layer and the silicon substrate being formed a silicon oxide layer,(b) subjecting the silicon substrate to an isotropic etching using the silicon nitride layer as a mask to form a recess on the substrate, the recess extending to and under the side wall of the silicon nitride layer, and(c) forming a channel stopper region by implanting an impurity into the silicon substrate through the recess-formed surface, and thereafter growing and forming a LOCOS layer on the recess-formed surface to obtain an isolation region.

Abstract: A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.

Abstract: A semiconductor memory device composed of a DRAM, an EEPROM, a mode switch means for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer means for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated.

Abstract: A semiconductor device includes a DRAM section constituting one MOS transistor and one capacitor, and an EEPROM section constituting one FLOTOX MOS transistor. A control gate electrode of the FLOTOX MOS transistor is connected to a source area of the MOS transistor of the DRAM section, on which is placed a capacitor electrode through an insulation layer, so that the control gate is made a storage node of the DRAM section. Thus, a combination of EEPROM cell and DRAM cell provides a NVRAM cell. When a data change is desired, the NVRAM cell works as DRAM. On the other hand, when data is to be preserved for a longer time, the data is transferred from DRAM section to EEPROM section by the NVRAM cell to be stored in EEPROM section. Since the capacitor of DRAM section has its storage node in common with a control gate of EEPROM section, the number of elements per cell can be reduced, thereby satisfying the requirement for applications of NVRAM cell to high density devices.

Abstract: An improved semiconductor memory device combining a volatile semiconductor storage with a nonvolatile semiconductor storage is disclosed. A capacitor for storing data in the volatile semiconductor storage is formed in a stack structure having a accumulation node polysilicon layer held in ohmic contact with the drain area of the nonvolatile semiconductor storage, an insulation film and a capacitor gate sequentially laminated one over the other on the nonvolatile semiconductor storage. The memory cell size can be minimized for high density applications thereof, with a longer data retention time achieved in the volatile semiconductor storage.

Abstract: A semiconductor memory device comprising a DRAM, an EEPROM, a mode switch for selecting either mode of the DRAM mode and the EEPROM mode, and a transfer circuit for transferring data stored in the DRAM to the EEPROM and vice versa. The DRAM consists of one transistor and one capacitor, and one of the terminals of the capacitor is electrically isolated.