Abstract: An image sensor circuit includes a plurality of column analog/digital conversion circuits each including: first to n-th storage elements configured to respectively store first to n-th pieces of bit data that constitute analog/digital-converted data obtained by analog/digital-converting analog signals outputted by pixels, where n is an integer greater than or equal to 2; first to (n?1)-th transfer paths configured to respectively transfer the bit data stored in the first to (n?1)-th storage elements from the first to (n?1)-th storage elements to the second to n-th storage elements; and an n-th transfer path configured to transfer the bit data stored in the n-th storage element from the n-th storage element to outside the plurality of column analog/digital conversion circuits.

Abstract: A multi-bit gray code generation circuit includes: a zeroth bit gray code generation circuit configured to generate a gray code corresponding to a bit 0 of a multi-bit gray code; and a plurality of gray code generation circuits each configured to generate a gray code corresponding to each bit higher than the bit 0 of the multi-bit gray code. Each of the plurality of gray code generation circuits is constituted by a plurality of flip-flop circuits. An output of a flip-flop circuit in the previous stage is input to a flip-flop circuit of the next stage. An output of a flip-flop circuit of the final stage is inverted and held by a flip-flop circuit of the first stage. An output of one of the plurality of flip-flop circuits is output as a gray code corresponding to each bit.

Abstract: An AD conversion circuit provided in a solid-state image sensor includes a counter circuit that performs count processing and a first latch circuit that holds at least one of a discrimination result of a first comparison circuit and a first output result of the counter circuit.

Abstract: A multi-bit gray code generation circuit includes: a zeroth bit gray code generation circuit configured to generate a gray code corresponding to a bit 0 of a multi-bit gray code; and a plurality of gray code generation circuits each configured to generate a gray code corresponding to each bit higher than the bit 0 of the multi-bit gray code. Each of the plurality of gray code generation circuits is constituted by a plurality of flip-flop circuits. An output of a flip-flop circuit in the previous stage is input to a flip-flop circuit of the next stage. An output of a flip-flop circuit of the final stage is inverted and held by a flip-flop circuit of the first stage. An output of one of the plurality of flip-flop circuits is output as a gray code corresponding to each bit.

Abstract: A solid-state image sensing device is of a global-shutter type and includes a vertical driving unit and an analog-to-digital (AD) converter. The vertical driving unit performs a shutter operation during a time period from when the AD converter starts an AD conversion to when the AD converter ends the AD conversion. The AD converter does not output a digital signal during a time period from when the vertical driving unit starts the shutter operation to when the vertical driving unit ends the shutter operation.

Abstract: An AD conversion circuit provided in a solid-state image sensor includes a counter circuit that performs count processing and a first latch circuit that holds at least one of a discrimination result of a first comparison circuit and a first output result of the counter circuit.

Abstract: Pixels, a charge storage element, a comparison signal generator that generates comparison signals, and a first analog-to-digital converter circuit that performs analog-to-digital conversion are included. The comparison signal generator generates the comparison signals such that a waveform having a voltage value that ranges from an upper limit to a lower limit and that has linearity and continuity is formed by connecting waveforms of the comparison signals to each other.

Abstract: Pixels, a charge storage element, a comparison signal generator that generates comparison signals, and a first analog-to-digital converter circuit that performs analog-to-digital conversion are included. The comparison signal generator generates the comparison signals such that a waveform having a voltage value that ranges from an upper limit to a lower limit and that has linearity and continuity is formed by connecting waveforms of the comparison signals to each other.

Abstract: A solid-state image sensing device is of a global-shutter type and includes a vertical driving unit and an analog-to-digital (AD) converter. The vertical driving unit performs a shutter operation during a time period from when the AD converter starts an AD conversion to when the AD converter ends the AD conversion. The AD converter does not output a digital signal during a time period from when the vertical driving unit starts the shutter operation to when the vertical driving unit ends the shutter operation.

Abstract: [Object] To prevent code skipping in decoding. [Solution] Included are a low-order bit latch unit (63) that latches digital code data as a low-order bit, a high-order bit counter unit (64) that counts one or both of edges of a control signal corresponding to a reference clock, and stops counting of high-order bits, triggered by output of a comparator (62) being inverted, a low-order bit decoding signal latch unit (65) that latches a low-order bit decoding signal, and a signal processing unit (8).

Abstract: There is provided a solid-state imaging apparatus including a driving device that reads image data from an imaging unit. When reading the image data from the imaging unit, the driving device renders the image data composed of image data having V rows and H columns and blanking data having V? rows and H? columns, and renders the amount of the image data changeable for at least every one frame.

Abstract: An internal voltage veneration circuit includes negative voltage generation circuits of a first type and a second type, and the negative voltage generation circuits of the first type and the second type are connected parallel to each other. A drive signal is input to a charge pump circuit from a signal drive circuit in opposite phases in the negative voltage generation circuits of the first type and in the negative voltage generation circuits of the second type. A plurality of pairs of a negative voltage generation circuit of the first type and a negative voltage generation circuit of the second type are disposed, and the negative voltage generation circuit of the first type and the negative voltage generation circuit of the second type are located adjacent to each other.

Abstract: [Object] To prevent code skipping in decoding. [Solution] Included are a low-order bit latch unit (63) that latches digital code data as a low-order bit, a high-order bit counter unit (64) that counts one or both of edges of a control signal corresponding to a reference clock, and stops counting of high-order bits, triggered by output of a comparator (62) being inverted, a low-order bit decoding signal latch unit (65) that latches a low-order bit decoding signal, and a signal processing unit (8).

Abstract: An internal voltage veneration circuit includes negative voltage generation circuits of a first type and a second type, and the negative voltage generation circuits of the first type and the second type are connected parallel to each other. A drive signal is input to a charge pump circuit from a signal drive circuit in opposite phases in the negative voltage generation circuits of the first type and in the negative voltage generation circuits of the second type. A plurality of pairs of a negative voltage generation circuit of the first type and a negative voltage generation circuit of the second type are disposed, and the negative voltage generation circuit of the first type and the negative voltage generation circuit of the second type are located adjacent to each other.

Abstract: There is provided a solid-state imaging apparatus including a driving device that reads image data from an imaging unit. When reading the image data from the imaging unit, the driving device renders the image data composed of image data having V rows and H columns and blanking data having V? rows and H? columns, and renders the amount of the image data changeable for at least every one frame.

Abstract: An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.

Abstract: An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.

Abstract: A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Abstract: There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Abstract: A semiconductor memory device comprises a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected and supplies a predetermined second voltage which is different from the fist voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection line separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout.