Abstract: There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Abstract: A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes (i) a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, (ii) a channel region provided under the gate electrode, (iii) diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and (iv) memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit includes an addressing arrangement for a single chip memory including cells associated with a plurality of redundant lines. A decoder for selecting a redundant row is selected by an address signal, and the decoder is programmed.

Abstract: A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane.

Abstract: The present invention provides a semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor storage device is provided with a gate electrode, a semiconductor layer, a gate insulating film sandwiched between the gate electrode and the semiconductor layer, a channel region under the gate electrode, diffusion regions provided respectively on two sides of the channel regions and being of the other conductivity region than the channel region, memory elements 1 provided respectively on two sides of the gate electrode and having a function of holding charges, and a word line driver circuit, in which the CMOS technique is used. The driver circuit includes a common node for supplying a potential for activating an output inverter for driving a row word line. While the semiconductor storage device is in a read mode, a CMOS inverter other than the output inverter controls a signal at the common node, the CMOS inverter connected to a read input line.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements. Each memory element comprises a gate electrode, a channel region, first and second diffusion regions, and first and second memory function sections provided an opposite aides of the gate electrode and having a function of retaining charges. The device further comprises a row decoder for selecting a word line in accordance with a row address, and a write control circuit for applying a write pulse to a bit line, which is connected to one of the first and second diffusion regions of the memory element connected to the selected word line, in accordance with a column address.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising a plurality of memory elements, a section for performing an erase or program operation with respect to the memory array, a section for receiving a suspend command, and in response to the suspend command, suspending the erase or program operation, and a section for receiving a resume command, and in response to the resume command, resuming the suspended erase or program operation. Each of the plurality of memory elements comprises a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, diffusion regions provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor memory device includes a memory cell array in which plural memory cells are arranged, a memory operation circuit, connected to the memory cell array, for executing a memory operation on the memory cell array, and a command controller, connected to the memory operation circuit, for receiving a command from the outside and generating a predetermined control signal to the memory operation circuit on the basis of the received command to control execution of the memory operation by the memory operation circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation, with respect to one of the memory elements, to the memory element via a bit line connected thereto, and thereafter, applying a second voltage for verifying whether or not the write or erase operation has been performed, to the memory element via the bit line, and a reset portion for grounding the bit line connected to the memory element after the write state machine has applied the first voltage and before the write state machine has applied the second voltage. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Abstract: A semiconductor storage device to provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect to the memory array, a decoder for decoding a signal indicating a current state of the write state machine, which is output from the write state machine, and outputting a status signal indicating a status of the program or erase operation with respect to the memory array, a status register for storing the status signal, and an output circuit for outputting the status signal stored in the status register. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the f

Abstract: A semiconductor memory device includes: a plurality of nonvolatile memory cells; a first load cell for generating a read voltage relative to a read current during reading from a selected nonvolatile memory cell; a reference cell for storing a reference state corresponding to a reference current of the selected nonvolatile memory cell; a second load cell for generating a voltage based on the reference current through the reference cell; and a programming circuit for generating a reference voltage equal to a voltage obtained from a specific current-voltage characteristic of the first load cell with respect to the reference current and programming the reference cell so as to equalize the voltage of the second load cell with the reference voltage, thereby to compensate for variations in the first load cell.

Abstract: A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references respectively corresponding to first and second voltages; applying a programming voltage to the memory cell; sensing a threshold voltage level of the memory cell; and comparing the sensed threshold voltage level with the first and second references and, in the case where the threshold voltage level is higher than the first reference and lower than the second reference, indicating that the memory cell is programmed into the desired state, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region formed below the gate electrode, a source and a drain as diffusion regions formed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of re

Abstract: A semiconductor memory device comprising: (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundan

Abstract: A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for writing from a plurality of planes in which memory cells are arranged in an array, an address selection circuit disposed for each of the planes, and an address buffer circuit for simultaneously providing a write address and a read address. Each of the address selection circuits is configured so as to be able to receive one of the read selection signals and one of the write selection signals from the control logic circuit.

Abstract: This invention is a method of improving a data retention ability of a semiconductor memory device having a plurality of nonvolatile memory cells storing a plurality of memory states. The method includes the steps of: (a) selecting the nonvolatile memory cells in a first memory group each of which accumulates charges higher in level than a first threshold from the plurality of nonvolatile memory cells; (b) extracting the nonvolatile memory cells in a first sub-group each of which accumulates the charges lower in level than a second threshold from the nonvolatile memory cells in the first memory group; and (c) programming the nonvolatile memory cells in the first sub-group until each of the nonvolatile memory cells accumulates the charges higher in level than the second threshold.

Abstract: A semiconductor memory device includes a controller for programming a nonvolatile memory cell by applying a first pulse so that a first amount of charge which is smaller than a target amount of charge is accumulated in the nonvolatile memory cell, a second pulse train of pulses so that a second amount of charge which is smaller than the target amount of charge and larger than the first amount of charge is accumulated in the nonvolatile memory cell, a third pulse train of pulses so that a third amount of charge which falls within an allowable error range of the target amount of charge is accumulated in the nonvolatile memory cell.

Abstract: A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period “a” of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor memory device of the present invention includes a first memory array, a first address register for storing therein a first address of the first memory array, a second memory array, a second address register for storing therein a second address of the second memory array, a multiplexer connected to the first memory array and the second memory array and to a memory output unit for selectively outputting the first memory array or the second memory array, and an array selection circuit for selecting the first memory array for re-programming in accordance with an input address and selecting the second memory array for a reading operation. The array selection circuit sends the first address to the, first address register, sends the second address to the second address register, and further, controls the multiplexer, so as to allow the second memory array to be connected to the memory output unit during re-programming of the first memory array.