Patents by Inventor Yoshinobu Miyamoto
Yoshinobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190312228Abstract: A first protruding portion that has a surface having liquid-philic properties to an ink material and has a frame shape and a second protruding portion that has a surface having liquid-repellent properties to the ink material, surrounds the first protruding portion such that at least a part of the first protruding portion is located inside, and has a frame shape are formed so as to surround an electro-optical element. Then, the ink material is applied to a region surrounded by the first protruding portion and is cured, and thus an organic layer that seals the electro-optical element is formed.Type: ApplicationFiled: July 14, 2017Publication date: October 10, 2019Inventors: Tohru SONODA, Hisao OCHI, Jumpei TAKAHASHI, Tohru SENOO, Takeshi HIRASE, Takashi OCHI, Akihiro MATSUI, Yoshinobu MIYAMOTO
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Patent number: 9142573Abstract: Each of the auxiliary capacitors (6a) includes a capacitor line (11b) comprised of the same material as the gate electrode (11a) and provided in the same layer as the gate electrode (11a), the gate insulating film (12) provided so as to cover the capacitor line (11a), a capacitor intermediate layer (13c) provided using the oxide semiconductor and provided on the gate insulating film (12) so as to overlap the capacitor line (11b), and a capacitor electrode (15b) provided on the capacitor intermediate layer (13c), and the capacitor intermediate layer (13c) is conductive.Type: GrantFiled: February 14, 2011Date of Patent: September 22, 2015Assignee: Sharp Kabushiki KaishaInventors: Tetsuya Yamashita, Tokuo Yoshida, Yoshimasa Chikama, Yoshifumi Ohta, Yuuji Mizuno, Hinae Mizuno, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto
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Patent number: 9035295Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).Type: GrantFiled: April 5, 2011Date of Patent: May 19, 2015Assignee: Sharp Kabushiki KaishaInventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
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Patent number: 8975619Abstract: The invention relates to co-activated silicate based phosphors. The invention further relates to the method of preparing these phosphors and to the use of these phosphors in electronic and electrooptical devices, in particular in light emitting diodes (LEDs) and solar cells. The invention further relates to illumination units comprising said phosphors.Type: GrantFiled: July 28, 2011Date of Patent: March 10, 2015Assignee: Merck Patent GmbHInventors: Hiroshi Okura, Takeo Wakimoto, Koutoku Ohmi, Yoshinobu Miyamoto
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Patent number: 8698152Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).Type: GrantFiled: February 14, 2011Date of Patent: April 15, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
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Patent number: 8592811Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).Type: GrantFiled: February 14, 2011Date of Patent: November 26, 2013Assignee: Sharp Kabushiki KaishaInventors: Masahiko Suzuki, Yoshimasa Chikama, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
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Publication number: 20130207114Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).Type: ApplicationFiled: February 14, 2011Publication date: August 15, 2013Inventors: Masahiko Suzuki, Yoshimasa Chikama, Yuuji Mizuno, Hinae Mizuno, Yoshifumi Ohta, Tokuo Yoshida, Okifumi Nakagawa, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Tetsuya Yamashita
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Publication number: 20130153882Abstract: The invention relates to co-activated silicate based phosphors. The invention further relates to the method of preparing these phosphors and to the use of these phosphors in electronic and electrooptical devices, in particular in light emitting diodes (LEDs) and solar cells. The invention further relates to illumination units comprising said phosphors.Type: ApplicationFiled: July 28, 2011Publication date: June 20, 2013Applicant: MERCK PATENT GESELLSCHAFT MIT BESCHRANKTER HAFTUNGInventors: Hiroshi Okura, Takeo Wakimoto, Koutoku Ohmi, Yoshinobu Miyamoto
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Publication number: 20130134411Abstract: A semiconductor device (100A) according to the present invention includes an oxide semiconductor layer (31a), first and second source electrodes (52a1 and 52a2), and first and second drain electrodes (53a1 and 53a2). The second source electrode (52a2) is formed to be in contact with a top surface of the first source electrode and inner to the first source electrode (52a1). The second drain electrode (53a2) is formed to be in contact with a top surface of the first drain electrode (53a1) and inner to the first drain electrode (53a1). The oxide semiconductor layer (31a) is formed to be in contact with the top surface of the first source electrode (52a1) and the top surface of the first drain electrode (53a1).Type: ApplicationFiled: April 5, 2011Publication date: May 30, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Okifumi Nakagawa, Yoshifumi Ohta, Yoshimasa Chikama, Tsuyoshi Inoue, Masahiko Suzuki, Michiko Takei, Yoshiyuki Harumoto, Yoshinobu Miyamoto, Hinae Mizuno
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Publication number: 20130112970Abstract: A TFT substrate (30a) including a TFT (5a) having: a gate electrode (14a) provided on a substrate (10a); a gate insulating film (15) provided to cover the gate electrode (14a); a semiconductor layer (16a) made of an oxide semiconductor provided on the gate insulating film (15) with a channel region (C) arranged to lie above the gate electrode (14a): and a source electrode (19aa) and a drain electrode (19b) provided on the semiconductor layer (16a) to be spaced from each other with the channel region (C) therebetween. A recess (R) is provided on the surface of the channel region (C) of the semiconductor layer (16a) to extend in the channel width direction.Type: ApplicationFiled: June 6, 2011Publication date: May 9, 2013Inventors: Yoshinobu Miyamoto, Okifumi Nakagawa, Yoshifumi Ohta, Yuuji Mizuno, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Yoshiyuki Harumoto, Tetsuya Yamashita
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Publication number: 20130056741Abstract: A display panel (50a) includes a TFT substrate (20a) in which a plurality of TFTs (5a) are provided, a counter substrate (30a) provided to face the TFT substrate (20a), and a display medium layer (40) provided between the TFT substrate (20a) and the counter substrate (30a), a plurality of pixels being provided so that each of the plurality of pixels is associated with a corresponding one of the TFTs (5a), wherein an oxide semiconductor layer (13) is provided in each of the TFTs (5a) as a channel, and an ultraviolet light absorbing layer (22) having a light transmitting property is provided in each of the pixels (P) so as to overlap the oxide semiconductor layer (13).Type: ApplicationFiled: February 14, 2011Publication date: March 7, 2013Applicants: SHARP KABUSHIKI KAISHAInventors: Yoshiyuki Harumoto, Yoshifumi Ohta, Yoshimasa Chikama, Tokuo Yoshida, Masahiko Suzuki, Okifumi Nakagawa, Yoshinobu Miyamoto, Tetsuya Yamashita, Hinae Mizuno
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Patent number: 8299487Abstract: A white light emitting device includes a semiconductor light emitting element that has a peak of an emission spectrum in a range of 370 nm to 480 nm, and at least one kind of phosphor that is excited by light emitted from the semiconductor light emitting element to emit visible light. The phosphor is represented by the formula: Sr1-x-yBaxSi2O2N2:Eu2+y, wherein x is in the range of 0.3<x<1.0, y is in the range of 0.03<y<0.3, and x+y is in the range of x+y<1.0, and a vehicle lamp using the while light emitting device.Type: GrantFiled: February 18, 2009Date of Patent: October 30, 2012Assignee: Koito Manufacturing Co., Ltd.Inventors: Hisayoshi Daicho, Masanobu Mizuno, Hajime Yamamoto, Yoshinobu Miyamoto, Bonggoo Yun
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Publication number: 20100320495Abstract: A white light emitting device includes a semiconductor light emitting element that has a peak of an emission spectrum in a range of 370 nm to 480 nm, and at least one kind of phosphor that is excited by light emitted from the semiconductor light emitting element to emit visible light. The phosphor is represented by the formula: Sr1-x-yBaxSi2O2N2:Eu2+y, wherein x is in the range of 0.3<x<1.0, y is in the range of 0.03<y<0.3, and x+y is in the range of x+y<1.0, and a vehicle lamp using the while light emitting device.Type: ApplicationFiled: February 18, 2009Publication date: December 23, 2010Applicant: KOITO MANUFACTURING CO., LTD.Inventors: Hisayoshi Daicho, Masanobu Mizuno, Hajime Yamamoto, Yoshinobu Miyamoto, Bonggoo Yun
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Patent number: 6707024Abstract: A bias circuit for a photodetector by the present invention provides a bias voltage to the photodetector that performs electric current amplification according to the bias voltage supplied, and is characterized by comprising a power node and an auto-bias circuit that changes a time constant of the bias circuit for the photodetector according to an optical power received by the photodetector, the auto-bias circuit being connected between the power node and the photodetector, thereby reliability of operation of the photodetector is enhanced.Type: GrantFiled: December 6, 2001Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Yoshinobu Miyamoto, Nobuaki Sato, Setsuo Misaizu, Hisaya Sakamoto, Akimitsu Miyazaki
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Publication number: 20020043614Abstract: A bias circuit for a photodetector by the present invention provides a bias voltage to the photodetector that performs electric current amplification according to the bias voltage supplied, and is characterized by comprising a power node and an auto-bias circuit that changes a time constant of the bias circuit for the photodetector according to an optical power received by the photodetector, the auto-bias circuit being connected between the power node and the photodetector, thereby reliability of operation of the photodetector is enhanced.Type: ApplicationFiled: December 6, 2001Publication date: April 18, 2002Inventors: Yoshinobu Miyamoto, Nobuaki Sato, Setsuo Misaizu, Hisaya Sakamoto, Akimitsu Miyazaki
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Patent number: 4195246Abstract: There is disclosed a support structure for a directly-heated cathode in a cathode ray tube, for supporting the cathode by fastening the strip leads of the cathode to support rods piercing and rigidly fixed to a base of insulating material through resistance welding. The support rods are provided in their proper positions respectively with protrusions having top plane areas to be contacted with the surfaces of the strip leads and the cathode is supported by fastening the strip leads to the protrusions through resistance welding. The length of the top plane area of the protrusion extending in the direction along the width of the strip lead is 30 to 80% of the size of the width of the strip lead.Type: GrantFiled: October 10, 1978Date of Patent: March 25, 1980Assignee: Hitachi, Ltd.Inventors: Yukihiro Izumida, Kitaro Sasaki, Yoshinobu Miyamoto