Patents by Inventor Yoshinobu Nakamura

Yoshinobu Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12120915
    Abstract: A display device includes a drive transistor and a switching transistor formed by layering an inorganic insulating film, an oxide semiconductor layer, an upper gate insulating layer, an upper gate electrode, and an interlayer insulating film. The drive transistor and the switching transistor include an oxide semiconductor film formed of the oxide semiconductor layer and provided in an island shape corresponding to the drive transistor and an island shape corresponding to the switching transistor, and the oxide semiconductor film includes a channel region overlapping with the upper gate electrode corresponding to the oxide semiconductor film, and a source region and a drain region. The drive transistor is provided with a lower gate electrode and a lower gate insulating layer between the inorganic insulating film and the oxide semiconductor layer. The length of lower gate electrode is less than or equal to the length of upper gate electrode.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 15, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Yoshinobu Nakamura, Kayo Haruguchi
  • Publication number: 20240323501
    Abstract: An image pickup apparatus capable of efficiently cooling a recording medium stored therein while suppressing an increase in size of the image pickup apparatus. The image pickup apparatus comprising an image pickup apparatus main body, a grip part disposed in the image pickup apparatus main body and to be gripped when the image pickup apparatus is used, a control board provided to the image pickup apparatus main body and arranged substantially perpendicular to an optical axis direction, a storage part that is mounted on the control board in a position not overlapping the grip part as viewed in the optical axis direction, and that is capable of storing a recording medium, and a heat dissipation duct that is disposed in a position not overlapping the grip part as viewed in the optical axis direction and is thermally connected to the storage part.
    Type: Application
    Filed: March 19, 2024
    Publication date: September 26, 2024
    Inventors: YUTA NAKAMURA, YUKO TERUYA, HAYATO MANO, YOSHINOBU SHIBAYAMA
  • Publication number: 20240300256
    Abstract: An ink jet recording method is a method in which a cyan ink, a magenta ink, a black ink, and a yellow ink radiation that are curable inks are ejected from ink jet heads to attach the radiation curable inks to a recording medium. The method includes, in this order, a first step of attaching the cyan ink, the magenta ink, and the black ink onto the recording medium and applying temporary curing radiation to the recording medium and a second step of attaching the yellow ink onto the recording medium and applying full curing radiation to the recording medium without applying the temporary curing radiation.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 12, 2024
    Inventors: Kiyoshi NAKAMURA, Yoshinobu YOSHIDA, Chigusa SATO, Asako KUBOTA, Shohei NAMIKOSHI, Tsuyoshi SANO
  • Publication number: 20240292676
    Abstract: A first TFT includes: a first semiconductor layer of a polysilicon; and a first gate electrode on the first semiconductor layer via a first gate insulating film. A second TFT includes: a first conductive layer and a second conductive layer made of the same material, and provided in the same layer, as the first semiconductor layer; a second semiconductor layer of an oxide semiconductor on the first conductive layer and the second conductive layer; and a second gate electrode on the second semiconductor layer via the second gate insulating film.
    Type: Application
    Filed: August 18, 2021
    Publication date: August 29, 2024
    Inventors: Tadayoshi MIYAMOTO, Yoshinobu NAKAMURA, Toshihiro KANEKO
  • Patent number: 12036808
    Abstract: An ink jet recording method is a method in which a cyan ink, a magenta ink, a black ink, and a yellow ink radiation that are curable inks are ejected from ink jet heads to attach the radiation curable inks to a recording medium. The method includes, in this order, a first step of attaching the cyan ink, the magenta ink, and the black ink onto the recording medium and applying temporary curing radiation to the recording medium and a second step of attaching the yellow ink onto the recording medium and applying full curing radiation to the recording medium without applying the temporary curing radiation.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: July 16, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kiyoshi Nakamura, Yoshinobu Yoshida, Chigusa Sato, Asako Kubota, Shohei Namikoshi, Tsuyoshi Sano
  • Patent number: 11774819
    Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: October 3, 2023
    Assignee: Sharp Display Technology Corporation
    Inventors: Tadayoshi Miyamoto, Yoshitaka Koyama, Yoshinobu Nakamura, Toshihiro Kaneko
  • Publication number: 20230244114
    Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.
    Type: Application
    Filed: January 11, 2023
    Publication date: August 3, 2023
    Inventors: Tadayoshi MIYAMOTO, Yoshitaka KOYAMA, Yoshinobu NAKAMURA, Toshihiro KANEKO
  • Patent number: 11491568
    Abstract: A non-magnetic member, a first magnetic member and a second magnetic member are prepared. The first magnetic member and the second magnetic member are connected to the non-magnetic member. Then, a first bonding portion which bonds the non-magnetic member and the first magnetic member to each other, and a second bonding portion which bonds the non-magnetic member and the second magnetic member to each other are formed. A hot isostatic pressing process is performed to the non-magnetic member, the first magnetic member and the second magnetic member to establish diffusion-bond. Thereafter, the non-magnetic member, the first magnetic member and the second magnetic member are hollowed, and the first bonding portion and the second bonding portion are removed. Thereafter, the non-magnetic member becomes a non-magnetic body, the first magnetic member becomes a first magnetic body, the second magnetic member becomes a second magnetic body and a sleeve is obtained.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 8, 2022
    Assignee: HITACHI METALS, LTD.
    Inventor: Yoshinobu Nakamura
  • Patent number: 11437520
    Abstract: The transistor includes a first insulating film, an oxide semiconductor layer, a gate insulating film, an upper gate electrode, and a second insulating film being sequentially layered on a substrate, and the transistor includes a light blocking layer layered on the second insulating film and formed of metal. The light blocking layer is electrically connected to the upper gate electrode by interposing a gate contact hole provided in the second insulating film. The oxide semiconductor layer is configured such that a region overlapping with the upper gate electrode entirely overlaps with the light blocking layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 6, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Yoshinobu Nakamura
  • Patent number: 11342812
    Abstract: In an aspect of the motor of the present invention, the motor includes a shaft centered on a center axis extending in a predetermined direction, and a stator located radially outside of the shaft. The stator has a coil wound around the stator. The motor further includes a housing member having a substantially cylindrical shape with a bottom, where the housing member accommodates substantially the entire stator, and supports the shaft, a cooling medium with which the housing member is filled, where the stator and the coil is immersed in the cooling medium, and a rotor that rotates radially outside of the housing member with the center axis of the shaft as a rotation center.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 24, 2022
    Assignee: NIDEC CORPORATION
    Inventors: Yoshinobu Nakamura, Takaaki Bando, Daisuke Ogasawara, Tsutomu Furukawa, Kazutoshi Matsuda
  • Publication number: 20220115479
    Abstract: A display device includes a drive transistor and a switching transistor formed by layering an inorganic insulating film, an oxide semiconductor layer, an upper gate insulating layer, an upper gate electrode, and an interlayer insulating film. The drive transistor and the switching transistor include an oxide semiconductor film formed of the oxide semiconductor layer and provided in an island shape corresponding to the drive transistor and an island shape corresponding to the switching transistor, and the oxide semiconductor film includes a channel region overlapping with the upper gate electrode corresponding to the oxide semiconductor film, and a source region and a drain region. The drive transistor is provided with a lower gate electrode and a lower gate insulating layer between the inorganic insulating film and the oxide semiconductor layer. The length of lower gate electrode is less than or equal to the length of upper gate electrode.
    Type: Application
    Filed: September 18, 2018
    Publication date: April 14, 2022
    Inventors: TADAYOSHI MIYAMOTO, YOSHINOBU NAKAMURA, KAYO HARUGUCHI
  • Publication number: 20220093650
    Abstract: A display device includes a transistor including: a substrate; a lower electrode; a lower insulating film; an oxide semiconductor layer; a gate insulating film; and a gate electrode stacked on top of an other in a stated order. The gate electrode matches the gate insulating film in plan view. The oxide semiconductor layer includes: a channel region across the gate insulating film from the gate electrode; and a source region and a drain region provided to sandwich the channel region. The lower electrode extends to intersect with the oxide semiconductor layer in plan view. The lower electrode has: a source-side end face positioned toward the source region and overlap with the source region; and a drain-side end face positioned toward the drain region and overlap with the channel region.
    Type: Application
    Filed: February 4, 2019
    Publication date: March 24, 2022
    Inventors: TADAYOSHI MIYAMOTO, KAYO HARUGUCHI, YOSHINOBU NAKAMURA
  • Publication number: 20210057583
    Abstract: The transistor includes a first insulating film, an oxide semiconductor layer, a gate insulating film, an upper gate electrode, and a second insulating film being sequentially layered on a substrate, and the transistor includes a light blocking layer layered on the second insulating film and formed of metal. The light blocking layer is electrically connected to the upper gate electrode by interposing a gate contact hole provided in the second insulating film. The oxide semiconductor layer is configured such that a region overlapping with the upper gate electrode entirely overlaps with the light blocking layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 25, 2021
    Inventors: TADAYOSHI MIYAMOTO, YOSHINOBU NAKAMURA
  • Patent number: 10871331
    Abstract: A cooling device and a motor are provided. The cooling device that cools a heating element is provided with: a cooling chamber for cooling the heating element with a first cooling medium; a radiator chamber for releasing the heat of the first cooling medium to the outside; and a first connection path and a second connection path for connecting the cooling chamber and the radiator chamber. When part of the first cooling medium in the cooling chamber is gasified, at least part of the gasified first cooling medium moves into the first connection path, thus causing a circulation in which the first cooling medium in the cooling chamber flows into the radiator chamber via the first connection path, and the first cooling medium in the radiator chamber flows into the cooling chamber via the second connection path.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 22, 2020
    Assignees: NIDEC CORPORATION, NATIONAL UNIVERSITY CORPORATION YOKOHAMA NATIONAL UNIVERSITY
    Inventors: Quing Yu, Tatsuya Noda, Shunichi Tanaka, Yoshinobu Nakamura, Masato Nakanishi
  • Patent number: 10819190
    Abstract: A motor includes a rotor, a stator having a cylindrical shape, disposed on a radial-direction outer side of the rotor, and surrounding the rotor, and a housing having a cylindrical shape, disposed on the radial-direction outer side of the stator, and housing the rotor and the stator. The stator includes teeth disposed along a circumferential direction and extending in a radial direction, and coils wound around the teeth. A hermetically sealed chamber filled with a cooling medium is provided between the housing and the rotor. A space housing the rotor core is provided on a radial-direction inner side of the sealed chamber that includes an inner chamber housing the coils, outer chambers disposed on the radial-direction outer side of the inner chamber and extend in the circumferential direction, and upper and lower connection portions located vertically above or below a shaft and connect the inner chamber to the outer chambers.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 27, 2020
    Assignee: Nidec Corporation
    Inventor: Yoshinobu Nakamura
  • Patent number: 10800121
    Abstract: An object of the present invention is to provide a tire vulcanization method in which there is no air remained between a vulcanization mold and an unvulcanized tire in tire vulcanization, the unvulcanized tire easily fits the vulcanization mold and an occurrence of bareness is prevented. The present invention relates to a tire vulcanization process comprising an application process of applying a coating agent comprising powder on a surface of an unvulcanized tire and a vulcanization process of vulcanizing the unvulcanized tire obtained in the application process, a tire production method comprising the vulcanization method, and a tire produced by the tire production method.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: October 13, 2020
    Assignee: SUMITOMO RUBBER INDUSTRIES, LTD.
    Inventor: Yoshinobu Nakamura
  • Publication number: 20200177056
    Abstract: In an aspect of the motor of the present invention, the motor includes a shaft centered on a center axis extending in a predetermined direction, and a stator located radially outside of the shaft. The stator has a coil wound around the stator. The motor further includes a housing member having a substantially cylindrical shape with a bottom, where the housing member accommodates substantially the entire stator, and supports the shaft, a cooling medium with which the housing member is filled, where the stator and the coil is immersed in the cooling medium, and a rotor that rotates radially outside of the housing member with the center axis of the shaft as a rotation center.
    Type: Application
    Filed: September 28, 2018
    Publication date: June 4, 2020
    Inventors: Yoshinobu NAKAMURA, Takaaki BANDO, Daisuke OGASAWARA, Tsutomu FURUKAWA, Kazutoshi MATSUDA
  • Publication number: 20200147564
    Abstract: To provide a rubber extruder capable of efficiently removing volatile components in unvulcanized rubber without decreasing productivity of the unvulcanized rubber. The rubber extruder 1 is for extruding the unvulcanized rubber (G) while kneading. It includes a barrel 2 having an input port 5 for introducing the unvulcanized rubber (G) and a discharge port 6 for discharging the unvulcanized rubber (G), a screw 3, which is arranged in the barrel 2, for extruding the unvulcanized rubber (G), and a vent 4 for sucking out air in the barrel 2. The screw 3 has a dam portion 7 which locally controls an extrusion amount of the unvulcanized rubber (G), a first screw portion 8 defined between the input port 5 and the dam portion 7, and a second screw portion 9 defined between the dam portion 7 and the discharge port 6. An effective screw length (L1) of the first screw portion 8 is 50% or more of a total effective screw length (L) of the screw 3.
    Type: Application
    Filed: May 16, 2018
    Publication date: May 14, 2020
    Applicants: Sumitomo Rubber Industries, Ltd., Nakata Engineering Co., Ltd.
    Inventors: Tomoo TANAKA, Yoshinobu NAKAMURA, Masayuki SAKAMOTO, Tadasuke SATO, Ryusuke OTA, Hideaki TAKEUCHI, Masaaki MICHIBAYASHI, Makoto NODA
  • Patent number: 10640869
    Abstract: A method of manufacturing a semiconductor device, includes: supplying precursor gas into process chamber in which plural substrates are accommodated by sequentially performing: supplying inert gas at first inert gas flow rate from first nozzle into the process chamber; supplying the inert gas at second inert gas flow rate higher than the first inert gas flow rate from the first nozzle into the process chamber while supplying precursor gas from the first nozzle into the process chamber; and supplying the inert gas at the first inert gas flow rate from the first nozzle into the process chamber while the process chamber is evacuated from an upstream side of flow of the precursor gas; stopping supply of the precursor gas; removing the precursor gas remaining in the process chamber; supplying reaction gas from a second nozzle into the process chamber; and removing the reaction gas remaining in the process chamber.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Kazuyuki Okuda, Masayoshi Minami, Yoshinobu Nakamura, Kosuke Takagi, Yukinao Kaga, Yuji Takebayashi
  • Patent number: 10558097
    Abstract: In a demultiplexer circuit, each unit circuit includes at least n TFTs 30 and n branch lines connected with one video signal line. Each TFT 30 includes an oxide semiconductor layer 7, an upper gate electrode 11 provided on the oxide semiconductor layer with a gate insulating layer 9 interposed therebetween, and a first electrode 13 and a second electrode 15. The demultiplexer circuit further includes a first interlayer insulating layer 21 covering the oxide semiconductor layer and the upper gate electrode and a second interlayer insulating layer 23 provided on the first interlayer insulating layer. The first electrode 13 is provided between the first interlayer insulating layer 21 and the second interlayer insulating layer 23 and is in contact with the oxide semiconductor layer inside a first contact hole CH1 formed in the first interlayer insulating layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 11, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Yoshinobu Nakamura