Abstract: A semiconductor memory device comprises an address bus having plural bits for designating addresses included in a first address group assigned to a memory cell array and in a second address group assigned to plural test modes, a first address decoder for decoding addresses in the first address group, and a second address decoder for decoding addresses in the second address group. A test commanding section generates a test commanding signal responsive to any one of addresses assigned to plural test modes. The second decoder acting as a test mode selecting section is activated by the test commanding signal to generate a test mode selecting signal from addresses assigned to the test modes. A test performing section tests inside the memory device in one of the test modes based on the test mode selecting signal. Number of data items to be input for executing a test inside the memory device is reduced without increasing an external pins.

Abstract: In a semiconductor memory device including memory cells and redundancy memory cells, a redundancy decoder for accessing the redundancy memory cells and disabling a normal decoder for accessing the memory cells includes a test circuit for introducing a test signal into the redundancy decoder. When the test signal is active, the redundancy decoder is disabled in spite of receiving a redundancy address, and instead, the normal decoder is operated to thereby access the memory cells.