Patents by Inventor Yoshinori Kaya
Yoshinori Kaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200411683Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.Type: ApplicationFiled: June 18, 2020Publication date: December 31, 2020Inventors: Yoshinori KAYA, Katsumi EIKYU, Akihiro SHIMOMURA, Hiroshi YANAGIGAWA, Kazuhisa MORI
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Patent number: 10038059Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and formed in an n?-type semiconductor region over a base made of a p-type semiconductor. The coupling transistor has a resurf layer as a p-type semiconductor region and couples a lower-voltage circuit region to a higher-voltage circuit region to which a power supply potential higher than the power supply potential supplied to the lower-voltage circuit region is supplied. The semiconductor device has a p-type semiconductor region formed in the portion of the n?-type semiconductor region which surrounds the coupling transistor in plan view.Type: GrantFiled: July 7, 2016Date of Patent: July 31, 2018Assignee: Renesas Electronics CorporationInventors: Yoshinori Kaya, Yasushi Nakahara
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Patent number: 10008561Abstract: A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate.Type: GrantFiled: December 21, 2015Date of Patent: June 26, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Kaya, Yasushi Nakahara, Ryo Kanda, Tetsu Toda
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Patent number: 10008919Abstract: A method of controlling a power supply to a semiconductor device including a first region having a high-side drive circuit, a second region having a signal processing circuit, a low-side drive circuit and a voltage control circuit, and a separation region formed between the first and second regions and having a rectifying element, includes turning on a first control signal to the voltage control circuit, turning off the first control signal to the voltage control circuit, and repeating the turning on of the first control signal and the turning off the first control signal.Type: GrantFiled: February 12, 2016Date of Patent: June 26, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Kaya, Yasushi Nakahara, Azuma Araya, Ryo Kanda, Tomonobu Kurihara, Tetsu Toda
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Publication number: 20180033854Abstract: An object of the present invention is to improve the performance of a semiconductor device. A p-channel transistor formed in a separation region has a RESURF layer that functions as a current path, is formed in an epitaxial layer, and is a p-type semiconductor layer, and a buried layer that is overlapped with the RESURF layer in planar view, is formed under the RESURF layer, is sandwiched between a semiconductor substrate and the epitaxial layer, and is an p-type semiconductor layer.Type: ApplicationFiled: June 23, 2017Publication date: February 1, 2018Applicant: Renesas Electronics CorporationInventors: Yoshinori KAYA, Yasushi NAKAHARA
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Patent number: 9866207Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.Type: GrantFiled: December 21, 2016Date of Patent: January 9, 2018Assignee: Renesas Electronics CorporationInventors: Ryo Kanda, Tetsu Toda, Junichi Nakamura, Kazuyuki Umezu, Tomonobu Kurihara, Takahiro Nagatsu, Yasushi Nakahara, Yoshinori Kaya
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Publication number: 20170104474Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Ryo KANDA, Tetsu TODA, Junichi NAKAMURA, Kazuyuki UMEZU, Tomonobu KURIHARA, Takahiro NAGATSU, Yasushi NAKAHARA, Yoshinori KAYA
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Publication number: 20170062567Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a coupling transistor made of a p-channel MOSFET and formed in an n?-type semiconductor region over a base made of a p-type semiconductor. The coupling transistor has a resurf layer as a p-type semiconductor region and couples a lower-voltage circuit region to a higher-voltage circuit region to which a power supply potential higher than the power supply potential supplied to the lower-voltage circuit region is supplied. The semiconductor device has a p-type semiconductor region formed in the portion of the n?-type semiconductor region which surrounds the coupling transistor in plan view.Type: ApplicationFiled: July 7, 2016Publication date: March 2, 2017Inventors: Yoshinori KAYA, Yasushi NAKAHARA
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Patent number: 9559687Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.Type: GrantFiled: August 21, 2015Date of Patent: January 31, 2017Assignee: Renesas Electronics CorporationInventors: Ryo Kanda, Tetsu Toda, Junichi Nakamura, Kazuyuki Umezu, Tomonobu Kurihara, Takahiro Nagatsu, Yasushi Nakahara, Yoshinori Kaya
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Publication number: 20160164398Abstract: A method of controlling a power supply to a semiconductor device including a first region having a high-side drive circuit, a second region having a signal processing circuit, a low-side drive circuit and a voltage control circuit, and a separation region formed between the first and second regions and having a rectifying element, includes turning on a first control signal to the voltage control circuit, turning off the first control signal to the voltage control circuit, and repeating the turning on of the first control signal and the turning off the first control signal.Type: ApplicationFiled: February 12, 2016Publication date: June 9, 2016Inventors: Yoshinori Kaya, Yasushi Nakahara, Azuma Araya, Ryo Kanda, Tomonobu Kurihara, Tetsu Toda
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Patent number: 9356093Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.Type: GrantFiled: May 13, 2015Date of Patent: May 31, 2016Assignee: Renesas Electronics CorporationInventors: Yoshinori Kaya, Yasushi Nakahara
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Publication number: 20160148995Abstract: A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate.Type: ApplicationFiled: December 21, 2015Publication date: May 26, 2016Inventors: Yoshinori Kaya, Yasushi Nakahara, Ryo Kanda, Tetsu Toda
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Patent number: 9343453Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.Type: GrantFiled: May 15, 2015Date of Patent: May 17, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Ryo Kanda, Tetsu Toda, Yasushi Nakahara, Yoshinori Kaya
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Patent number: 9324862Abstract: To prevent a current leak in an impurity region surrounding a transistor, in a region where a portion, of a second conductivity type region, extending from a first circuit region side toward a second circuit region side and an element separation film overlap each other in plan view, a field plate and conductive films are provided alternately from the first circuit region side toward the second circuit region side in plan view. Further, in this region, there is a decrease in the potential of the field plate and the potentials of the conductive films from the first circuit region toward the second circuit region. Further, at least one of the conductive films has a potential lower than the potential of the field plate adjacent to the conductive film on the second circuit region side in plan view. Further, this conductive film covers at least a part of the second conductivity type region without space in the extension direction of the second conductivity type region.Type: GrantFiled: March 4, 2015Date of Patent: April 26, 2016Assignee: Renesas Electronics CorporationInventors: Yoshinori Kaya, Yasushi Nakahara, Ryo Kanda, Tetsu Toda
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Patent number: 9287256Abstract: Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.Type: GrantFiled: October 17, 2014Date of Patent: March 15, 2016Assignee: Renesas Electronics CorporationInventors: Yoshinori Kaya, Yasushi Nakahara, Azuma Araya, Ryo Kanda, Tomonobu Kurihara, Tetsu Toda
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Publication number: 20160056818Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.Type: ApplicationFiled: August 21, 2015Publication date: February 25, 2016Inventors: Ryo KANDA, Tetsu TODA, Junichi NAKAMURA, Kazuyuki UMEZU, Tomonobu KURIHARA, Takahiro NAGATSU, Yasushi NAKAHARA, Yoshinori KAYA
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Publication number: 20150270390Abstract: To prevent a current leak in an impurity region surrounding a transistor, in a region where a portion, of a second conductivity type region, extending from a first circuit region side toward a second circuit region side and an element separation film overlap each other in plan view, a field plate and conductive films are provided alternately from the first circuit region side toward the second circuit region side in plan view. Further, in this region, there is a decrease in the potential of the field plate and the potentials of the conductive films from the first circuit region toward the second circuit region. Further, at least one of the conductive films has a potential lower than the potential of the field plate adjacent to the conductive film on the second circuit region side in plan view. Further, this conductive film covers at least a part of the second conductivity type region without space in the extension direction of the second conductivity type region.Type: ApplicationFiled: March 4, 2015Publication date: September 24, 2015Inventors: Yoshinori Kaya, Yasushi Nakahara, Ryo Kanda, Tetsu Toda
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Publication number: 20150262990Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.Type: ApplicationFiled: May 15, 2015Publication date: September 17, 2015Inventors: Ryo KANDA, Tetsu TODA, Yasushi NAKAHARA, Yoshinori KAYA
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Publication number: 20150243731Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.Type: ApplicationFiled: May 13, 2015Publication date: August 27, 2015Inventors: Yoshinori KAYA, Yasushi NAKAHARA
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Patent number: 9054070Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.Type: GrantFiled: November 21, 2013Date of Patent: June 9, 2015Assignee: Renesas Electronics CorporationInventors: Yoshinori Kaya, Yasushi Nakahara