Patents by Inventor Yoshinori Kaya

Yoshinori Kaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9048213
    Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: June 2, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Kanda, Tetsu Toda, Yasushi Nakahara, Yoshinori Kaya
  • Publication number: 20150115342
    Abstract: Provided is a semiconductor device including a substrate of a first conductivity type, a first circuit region, a separation region, a second circuit region, and a rectifying element. The rectifying element has a second conductivity type layer, a first high concentration second conductivity type region, a second high concentration second conductivity type region, an element isolation film, a first insulation layer, and a first conductive film. A first contact is coupled to the first high concentration second conductivity type region, and a second contact is coupled to the second high concentration second conductivity type region. A third contact is coupled to the first conductive film. The first contact, the second contact and the third contact are separated from each other.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 30, 2015
    Inventors: Yoshinori KAYA, Yasushi NAKAHARA, Azuma ARAYA, Ryo KANDA, Tomonobu KURIHARA, Tetsu TODA
  • Patent number: 8952483
    Abstract: A potential isolation element is provided separately from a diode. An n-type low-concentration region is formed on a P-type layer. A first high-concentration N-type region is positioned in the n-type low-concentration region and is connected to a cathode electrode of the diode. A second high-concentration N-type region is positioned in the n-type low-concentration region, is disposed to be spaced from a first second-conduction-type high-concentration region, and is connected to a power supply interconnection of a first circuit. A first P-type region is formed in the n-type low-concentration region, and a bottom portion thereof is connected to the P-type layer. A ground potential is applied to the first P-type region, and the first P-type region is positioned in the vicinity of the first high-concentration N-type region.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Kaya, Yasushi Nakahara
  • Publication number: 20150008539
    Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 8, 2015
    Inventors: Ryo KANDA, Tetsu TODA, Yasushi NAKAHARA, Yoshinori KAYA
  • Publication number: 20140167207
    Abstract: A potential isolation element is provided separately from a diode. An n-type low-concentration region is formed on a P-type layer. A first high-concentration N-type region is positioned in the n-type low-concentration region and is connected to a cathode electrode of the diode. A second high-concentration N-type region is positioned in the n-type low-concentration region, is disposed to be spaced from a first second-conduction-type high-concentration region, and is connected to a power supply interconnection of a first circuit. A first P-type region is formed in the n-type low-concentration region, and a bottom portion thereof is connected to the P-type layer. A ground potential is applied to the first P-type region, and the first P-type region is positioned in the vicinity of the first high-concentration N-type region.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 19, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshinori KAYA, Yasushi NAKAHARA
  • Publication number: 20140167171
    Abstract: An isolation region includes an element isolation film and a field plate electrode. The field plate electrode overlaps the element isolation film and surrounds a first circuit when seen in a plan view. A part of the field plate electrode is also positioned on a connection transistor. A source and a drain of the connection transistor are opposite to each other through the field plate electrode when seen in a plan view. In addition, the field plate electrode is divided into a first portion including a portion that is positioned on the connection transistor, and a second portion other than the first portion.
    Type: Application
    Filed: November 21, 2013
    Publication date: June 19, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshinori Kaya, Yasushi Nakahara