Patents by Inventor Yoshinori Matsuura

Yoshinori Matsuura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961771
    Abstract: There is provided a laminated sheet with which the electrical inspection of a redistribution layer formed later can be efficiently performed, while the laminated sheet is in the form of a sheet useful for the formation of a redistribution layer. This laminated sheet includes a carrier with a release function; a first electrically conductive film provided on the carrier with the release function; an insulating film provided on the first electrically conductive film; and a second electrically conductive film provided on the insulating film. The second electrically conductive film is used for formation of a redistribution layer, and the first electrically conductive film, the insulating film, and the second electrically conductive film function as a capacitor for performing electrical inspection of the redistribution layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 16, 2024
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Takenori Yanai, Rintaro Ishii
  • Publication number: 20240080990
    Abstract: There is provided a wiring substrate whose mechanical strength, water resistance, humidity resistance, and product yield can be improved. This wiring substrate includes a device region in which a main wiring pattern composed of a metal layer is embedded in an insulating layer; a peripheral region which surrounds a periphery of the device region and in which a dummy wiring pattern composed of a metal layer is embedded in an insulating layer; and an insulating boundary region interposed between the device region and the peripheral region, composed of an insulating layer. The insulating boundary region has a winding shape in which it is possible to draw a virtual straight line alternately traversing the metal layer constituting the dummy wiring pattern and the insulating layer constituting the insulating boundary region, parallel to an inscribed line of at least one side of an outer edge of the device region.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 7, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Mikiko KOMIYA, Yoshinori MATSUURA
  • Publication number: 20240070144
    Abstract: An information processing device is an information processing device as any node among a plurality of nodes constituting a blockchain network extending over a plurality of areas, and includes: an area determination unit that determines an area to which each of the plurality of nodes belongs based on information registered for each of the plurality of nodes; and a selection unit that selects Outbound adjacent nodes among the Outbound adjacent nodes of a node related to the information processing device so that a number of nodes belonging to other areas with respect to an area to which the relevant node belongs is a constant number, thereby efficiently improving fairness between nodes of the blockchain network.
    Type: Application
    Filed: January 7, 2021
    Publication date: February 29, 2024
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Hiroshi MATSUURA, Yoshinori GOTO, Hidehiro SAO
  • Publication number: 20240034670
    Abstract: There is provided a carrier-attached metal foil in which the metal layer is less likely to be released at the ends of the carrier-attached metal foil or in the cutting place(s) of a downsized carrier-attached metal foil, and moreover a decrease in the strength of the carrier is effectively suppressed. This carrier-attached metal foil includes a carrier; a release layer provided on the carrier; and a metal layer having a thickness of 0.01 ?m or more and 4.0 ?m or less provided on the release layer. The carrier has a flat region having a developed interfacial area ratio Sdr of less than 5%, and an uneven region having a developed interfacial area ratio Sdr of 5% or more and 39% or less, on at least a surface on the metal layer side, and the uneven region is provided in a linear pattern surrounding the flat region.
    Type: Application
    Filed: November 29, 2021
    Publication date: February 1, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi NAKAMURA, Mikiko KOMIYA, Yoshinori MATSUURA
  • Publication number: 20230420270
    Abstract: There is provided a method for manufacturing a wiring substrate in which damage to a device layer during carrier release can be suppressed, and a photolithography process can be carried out with good accuracy on the device layer after carrier release. This method includes: providing a laminated sheet including a carrier, a release layer, a metal layer, and a device layer in order; making a cut line from a surface of the laminated sheet on the carrier side so that the cut line passes through the carrier, the release layer, and the metal layer when the laminated sheet is seen in a cross-sectional view; and removing outer edge portions outside the cut line in the carrier, the release layer, and the metal layer, thereby exposing part of a surface of the device layer on the metal layer side to form a pressurizable exposed portion for promoting release of the carrier.
    Type: Application
    Filed: August 6, 2021
    Publication date: December 28, 2023
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yukiko KITABATAKE, Takenori YANAI, Yoshinori MATSUURA
  • Patent number: 11765840
    Abstract: An extremely thin copper foil with a carrier is provided that can keep stable releasability even after being heated for a prolonged time at a high temperature of 350° C. or more. The extremely thin copper foil with a carrier includes a carrier composed of a glass or ceramic material; an intermediate layer provided on the carrier and composed of at least one metal selected from the group consisting of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, and Mo; a release layer provided on the intermediate layer and including a carbon sublayer and a metal oxide sublayer or containing metal oxide and carbon; and an extremely thin copper layer provided on the release layer.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 19, 2023
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Rintaro Ishii, Takenori Yanai, Yoshinori Matsuura
  • Patent number: 11756845
    Abstract: A glass carrier-attached copper foil is provided that can achieve a desired circuit mounting board that reduces separation of a copper layer at the cut edge even if the copper foil is downsized to dimensions enabling mount of a circuit, and has an intended circuit pattern with a fine pitch. The glass carrier-attached copper foil includes a glass carrier, a release layer, and a copper layer with a thickness of 0.1 to 3.0 ?m. The glass carrier has, at least on its surface having the copper layer thereon, a plurality of flat regions each having a maximum height Rz of less than 1.0 ?m as measured in accordance with JIS B 0601-2001 and a rough region having a maximum height Rz of 1.0 to 30.0 ?m as measured in accordance with JIS B 0601-2001. The rough region has a pattern of lines that define the flat regions.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 12, 2023
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Takenori Yanai, Toshimi Nakamura
  • Patent number: 11637358
    Abstract: Provided is a carrier-attached metal foil which has excellent carrier-releasability and excellent selective metal layer-etchability, and can achieve a reduction in transmission loss and resistance in a semiconductor package (for example, a millimeter-wave antenna substrate) manufactured using the same. The carrier-attached metal foil includes: (a) a carrier; (b) a release functional layer on the carrier and including (b1) an adhesion layer disposed closer to the carrier and having a thickness of more than 10 nm and less than 200 nm and (b2) a release assistance layer disposed farther from the carrier and having a thickness of 50 nm or more and 500 nm or less; and (c) a composite metal layer on the release functional layer and including (c1) a carbon layer disposed closer to the release assistance layer, and (c2) a first metal layer disposed farther from the release assistance layer and mainly composed of Au or Pt.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 25, 2023
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Mikiko Komiya, Takenori Yanai, Rintaro Ishii, Yoshinori Matsuura
  • Publication number: 20230072120
    Abstract: Provided is a carrier-attached metal foil which can suppress the number of foreign matter particles on the surface of a metal layer to enhance circuit formability, and can keep stable releasability even after heating at a high temperature of 240° C. or higher (for example, 260° C.) for a long period of time. The carrier-attached metal foil includes a carrier, a release functional layer provided on the carrier, the release functional layer including a metal oxynitride, and a metal layer provided on the release functional layer.
    Type: Application
    Filed: January 21, 2021
    Publication date: March 9, 2023
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yukiko KITABATAKE, Masahiro KOIDE, Rintaro ISHII, Yoshinori MATSUURA
  • Patent number: 11576267
    Abstract: An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 ?m or less/10 ?m or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: February 7, 2023
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventor: Yoshinori Matsuura
  • Patent number: 11527415
    Abstract: There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 13, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Tetsuro Sato, Takenori Yanai, Toshimi Nakamura
  • Patent number: 11525073
    Abstract: There is a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween, wherein an unoccupied region without the soluble adhesive layer is provided within a facing area where the reinforcing sheet faces the multilayer laminate; allowing a liquid capable of dissolving the soluble adhesive layer to infiltrate the unoccupied region to dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced to generate no large local warpage, thereby improving the reliable connection and the surface flatness (coplanarity) of the multilayer wiring layer. The used reinforcing sheet can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 13, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Tetsuro Sato, Toshimi Nakamura, Takenori Yanai
  • Publication number: 20220223456
    Abstract: Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.
    Type: Application
    Filed: May 18, 2020
    Publication date: July 14, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Toshimi NAKAMURA
  • Patent number: 11317522
    Abstract: Provided is a method of manufacturing a circuit board involves: preparing a composite laminate including a support, a release layer, and a multilayered circuit board; disposing the composite laminate on a stage such that one face of the composite laminate is put into tight contact with the stage; and releasing the support or the multilayered circuit board from the release layer such that the support or the multilayered circuit board forms a convex face with a curvature radius of 200 to 5000 mm while the face of the composite laminate is kept in tight contact with the stage. The method according to the present invention can prevent the occurrences of defects, for example, breaking in the support and cracking and wire disconnections in the multilayered circuit board in manufacturing of circuit boards, such as coreless circuit boards, and ensure stable release of the support or the multilayered circuit board.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 26, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Yoshinori Matsuura
  • Publication number: 20220022326
    Abstract: There is provided a laminate in which a decrease in the release function of a release layer can be suppressed even when the laminate is heat-treated under either temperature condition of low temperature and high temperature. This laminate includes a carrier; an adhesion layer on the carrier and containing a metal M1 having a negative standard electrode potential; a release-assisting layer on a surface of the adhesion layer opposite to the carrier and containing a metal M2 (M2 is a metal other than an alkali metal and an alkaline earth metal); a release layer on a surface of the release-assisting layer opposite to the adhesion layer; and a metal layer on a surface of the release layer opposite to the release-assisting layer, and T2/T1, a ratio of a thickness of the release-assisting layer, T2, to a thickness of the adhesion layer, T1, is more than 1 and 20 or less.
    Type: Application
    Filed: November 14, 2019
    Publication date: January 20, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Rintaro ISHII, Takenori YANAI, Yoshinori MATSUURA
  • Publication number: 20210328325
    Abstract: Provided is a carrier-attached metal foil which has excellent carrier-releasability and excellent selective metal layer-etchability, and can achieve a reduction in transmission loss and resistance in a semiconductor package (for example, a millimeter-wave antenna substrate) manufactured using the same. The carrier-attached metal foil includes: (a) a carrier; (b) a release functional layer on the carrier and including (b1) an adhesion layer disposed closer to the carrier and having a thickness of more than 10 nm and less than 200 nm and (b2) a release assistance layer disposed farther from the carrier and having a thickness of 50 nm or more and 500 nm or less; and (c) a composite metal layer on the release functional layer and including (c1) a carbon layer disposed closer to the release assistance layer, and (c2) a first metal layer disposed farther from the release assistance layer and mainly composed of Au or Pt.
    Type: Application
    Filed: November 19, 2019
    Publication date: October 21, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Mikiko KOMIYA, Takenori YANAI, Rintaro ISHII, Yoshinori MATSUURA
  • Publication number: 20210313237
    Abstract: There is provided a laminated sheet with which the electrical inspection of a redistribution layer formed later can be efficiently performed, while the laminated sheet is in the form of a sheet useful for the formation of a redistribution layer. This laminated sheet includes a carrier with a release function; a first electrically conductive film provided on the carrier with the release function; an insulating film provided on the first electrically conductive film; and a second electrically conductive film provided on the insulating film. The second electrically conductive film is used for formation of a redistribution layer, and the first electrically conductive film, the insulating film, and the second electrically conductive film function as a capacitor for performing electrical inspection of the redistribution layer.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 7, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori MATSUURA, Takenori YANAI, Rintaro ISHII
  • Publication number: 20210274650
    Abstract: There is provided a laminate that can suppress the warpage of a laminated product when used for the manufacture of the laminated product. This laminate includes a float glass substrate having a top surface and a bottom surface; and a metal layer provided on the top surface side of the float glass substrate.
    Type: Application
    Filed: May 11, 2021
    Publication date: September 2, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Rintaro ISHII, Toshimi NAKAMURA, Yoshinori MATSUURA
  • Patent number: 11071214
    Abstract: Provided is a method of manufacturing a multilayer wiring board, in which electrical inspection can be performed with accurate probing while warpage of a multilayer laminate is reduced. This method includes providing a laminated sheet including a first support, a first release layer and a metal layer; alternately stacking wiring layers and insulating layers on a surface of the metal layer, wherein an n-th wiring layer being the uppermost layer includes an n-th connection pad; bonding a second support having an opening on a surface, remote from the laminated sheet, of the multilayer laminate with a second release layer therebetween such that at least a part of the n-th connection pad is disposed within the opening; releasing the first support from the reinforced multilayer laminate at the first release layer; and putting conductors into contact with the n-th connection pads of the reinforced multilayer laminate to perform electrical inspection.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: July 20, 2021
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Yasuhiro Seto, Toshimi Nakamura
  • Publication number: 20210127503
    Abstract: An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 ?m or less/10 ?m or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 29, 2021
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventor: Yoshinori MATSUURA