Patents by Inventor Yoshinori Miyaki
Yoshinori Miyaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6777262Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: GrantFiled: March 13, 2003Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20040089923Abstract: Attaining improvement of the reliability and standardization of the lead frame.Type: ApplicationFiled: August 21, 2003Publication date: May 13, 2004Applicant: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20040051167Abstract: A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate 5 supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a 2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.Type: ApplicationFiled: August 21, 2003Publication date: March 18, 2004Applicant: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Patent number: 6692989Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: GrantFiled: February 24, 2003Date of Patent: February 17, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems, Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 6661081Abstract: Attaining improvement of the reliability and standardization of the lead frame. A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a≦2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.Type: GrantFiled: October 18, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20030136573Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: ApplicationFiled: March 13, 2003Publication date: July 24, 2003Applicant: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20030124770Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: ApplicationFiled: February 24, 2003Publication date: July 3, 2003Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 6558980Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.Type: GrantFiled: April 11, 2001Date of Patent: May 6, 2003Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 6553657Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: GrantFiled: October 23, 2002Date of Patent: April 29, 2003Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20030067067Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.Type: ApplicationFiled: November 18, 2002Publication date: April 10, 2003Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
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Patent number: 6541702Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device includes a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along lateral of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: GrantFiled: July 9, 2002Date of Patent: April 1, 2003Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20030037948Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: ApplicationFiled: October 23, 2002Publication date: February 27, 2003Applicant: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Publication number: 20020189835Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: ApplicationFiled: July 9, 2002Publication date: December 19, 2002Applicant: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Patent number: 6476479Abstract: A semiconductor device includes a semiconductor chip having a plurality of electrodes formed on a first major surface thereof, a resin package sealing the semiconductor chip therein, a plurality of leads electrically connected to the electrodes of the semiconductor chip and formed so as to extend inside and outside the resin package, and a support lead supporting the semiconductor chip at a part of a second major surface of the semiconductor chip opposite the first major surface. The semiconductor chip is bonded to the support lead with an adhesive tape.Type: GrantFiled: January 22, 2002Date of Patent: November 5, 2002Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Kazunari Suzuki, Daisuke Omoda
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Publication number: 20020146864Abstract: To improve a reflow characteristic and realize leadlessness. A semiconductor device comprises a cross die pad which supports a semiconductor chip and in which an area of the region joined to the semiconductor chip is smaller than that of the outer size thereof being smaller than the rear surface of the semiconductor chip; wires connected to pads of the semiconductor chip; a plurality of inner leads which are arranged around the semiconductor chip and in which a silver plating layer is formed at a wire bonding area; molding resin for resin sealing the semiconductor chip; a plurality of outer leads exposed from the molding resin and in which a lead-free metallic layer is formed on a contact surface, wherein the flat surface size of the molding resin is formed to be equal to or less than 28 mm×28 mm and the thickness thereof is formed to be 1.4 mm or less, and thereby it is possible to improve a reflow characteristic and realize leadlessness.Type: ApplicationFiled: April 4, 2002Publication date: October 10, 2002Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
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Patent number: 6444905Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device includes a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.Type: GrantFiled: December 9, 1999Date of Patent: September 3, 2002Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki
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Patent number: 6441400Abstract: A semiconductor device includes a semiconductor chip having a plurality of electrodes formed on a first major surface thereof, a resin package sealing the semiconductor chip therein, a plurality of leads electrically connected to the electrodes of the semiconductor chip and formed so as to extend inside and outside the resin package, and a support lead supporting the semiconductor chip at a part of a second major surface of the semiconductor chip opposite the first major surface. The semiconductor chip is bonded to the support lead with an adhesive tape.Type: GrantFiled: January 22, 2002Date of Patent: August 27, 2002Assignee: Hitachi, Ltd.Inventors: Yoshinori Miyaki, Kazunari Suzuki, Daisuke Omoda
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Publication number: 20020056905Abstract: A semiconductor device comprises a semiconductor chip having a plurality of electrodes formed in a first major surface thereof, a resin package sealing the semiconductor chip therein, a plurality leads electrically connected to the electrodes of the semiconductor chip and formed so as to extend inside and outside the resin package, and a support lead supporting the semiconductor chip at a part of a second major surface of the semiconductor chip opposite the first major surface. The semiconductor chip is bonded to the support lead with an adhesive tape.Type: ApplicationFiled: January 22, 2002Publication date: May 16, 2002Inventors: Yoshinori Miyaki, Kazunari Suzuki, Daisuke Omoda
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Publication number: 20020056904Abstract: A semiconductor device comprises a semiconductor chip having a plurality of electrodes formed in a first major surface thereof, a resin package sealing the semiconductor chip therein, a plurality leads electrically connected to the electrodes of the semiconductor chip and formed so as to extend inside and outside the resin package, and a support lead supporting the semiconductor chip at a part of a second major surface of the semiconductor chip opposite the first major surface. The semiconductor chip is bonded to the support lead with an adhesive tape.Type: ApplicationFiled: January 22, 2002Publication date: May 16, 2002Inventors: Yoshinori Miyaki, Kazunari Suzuki, Daisuke Omoda
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Publication number: 20020047189Abstract: Attaining improvement of the reliability and standardization of the lead frame.Type: ApplicationFiled: October 18, 2001Publication date: April 25, 2002Inventors: Yoshinori Miyaki, Hiromichi Suzuki