Patents by Inventor Yoshinori Miyaki

Yoshinori Miyaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6340837
    Abstract: A semiconductor device includes a semiconductor chip having a plurality of electrodes formed on a first major surface thereof, a resin package sealing the semiconductor chip therein, of leads electrically connected to the electrodes of the semiconductor chip and formed so as to extend inside and outside the resin package, and a support lead supporting the semiconductor chip at a part of a second major surface of the semiconductor chip opposite the first major surface. The semiconductor chip is bonded to the support lead with an adhesive tape.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: January 22, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Kazunari Suzuki, Daisuke Omoda
  • Patent number: 6291273
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: September 18, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20010018264
    Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.
    Type: Application
    Filed: May 9, 2001
    Publication date: August 30, 2001
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20010015481
    Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 23, 2001
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20010010949
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 2, 2001
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20010008779
    Abstract: A semiconductor device comprising: a tape substrate which supports a semiconductor chip, said chip having surface electrodes, said tape substrate being provided with a plurality of leads corresponding to the surface electrodes of the semiconductor chip and bonded thereto, and with dummy leads formed in vacant regions in corner portions of the tape substrate where the leads are not formed; conductive members for bonding the surface electrodes of the semiconductor chip to the leads of the tape substrate; and a plurality of external terminals arranged on an outside periphery of the semiconductor chip and mounted on the tape substrate.
    Type: Application
    Filed: March 14, 2001
    Publication date: July 19, 2001
    Inventors: Yoshinori Miyaki, Yasuhisa Hagiwara, Seiichi Ichihara, Hisao Nakamura, Hidenori Suzuki
  • Publication number: 20010006251
    Abstract: A semiconductor device comprising: a tape substrate which supports a semiconductor chip, said chip having surface electrodes, said tape substrate being provided with a plurality of leads corresponding to the surface electrodes of the semiconductor chip and bonded thereto, and with dummy leads formed in vacant regions in corner portions of the tape substrate where the leads are not formed; conductive members for bonding the surface electrodes of the semiconductor chip to the leads of the tape substrate; and a plurality of external terminals arranged on an outside periphery of the semiconductor chip and mounted on the tape substrate.
    Type: Application
    Filed: December 22, 2000
    Publication date: July 5, 2001
    Inventors: Yoshinori Miyaki, Yasuhisa Hagiwara, Seiichi Ichihara, Hisao Nakamura, Hidenori Suzuki
  • Patent number: 5637913
    Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: June 10, 1997
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.
    Inventors: Yujiro Kajihara, Kazunari Suzuki, Kunihiro Tsubosaki, Hiromichi Suzuki, Yoshinori Miyaki, Takahiro Naito, Sueo Kawai
  • Patent number: 5378656
    Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: January 3, 1995
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.
    Inventors: Yujiro Kajihara, Kazunari Suzuki, Kunihiro Tsubosaki, Hiromichi Suzuki, Yoshinori Miyaki, Takahiro Naito, Sueo Kawai