Patents by Inventor Yoshinori Momonoi

Yoshinori Momonoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9123504
    Abstract: Provided are a semiconductor inspection device and a semiconductor inspection method such that in a specimen image in a single field of view obtained by an electron microscope, it is possible to suppress variations in the edge position measurement error attributable to the materials and structures of the lower layers of measured patterns by a first method, wherein the area in the field of view obtained by electron beam scanning is divided into a plurality of regions on the basis of information regarding the structures and materials of the object to be observed and the electron beam scanning conditions are changed for individual regions (805, 806), a second method, wherein, the image processing conditions are changed for individual regions resulting from division of the obtained images, or a third method, wherein the edge detection conditions are changed for individual regions resulting from the division within the edge inspection regions of the obtained images.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: September 1, 2015
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Atsuko Yamaguchi, Yoshinori Momonoi, Junichi Tanaka, Hiroki Kawada
  • Publication number: 20150008322
    Abstract: An object of the invention is to provide a scanning electron microscope which forms an electric field to lift up, highly efficiently, electrons discharged from a hole bottom or the like even if a sample surface is an electrically conductive material. To achieve the above object, according to the invention, a scanning electron microscope including a deflector which deflects a scanning position of an electron beam, and a sample stage for loading a sample thereon, is proposed. The scanning electron microscope includes a control device which controls the deflector or the sample stage in such a way that before scanning a beam on a measurement target pattern, a lower layer pattern situated in a lower layer of the measurement target pattern undergoes beam irradiation on another pattern situated in the lower layer.
    Type: Application
    Filed: February 18, 2013
    Publication date: January 8, 2015
    Inventors: Toshiyuki Yokosuka, Chahn Lee, Hideyuki Kazumi, Hiroshi Makino, Yuzuru Mizuhara, Miki Isawa, Michio Hatano, Yoshinori Momonoi
  • Publication number: 20130321610
    Abstract: There is provided a technique to correctly select and measure a pattern to be measured even when contours of the pattern are close to each other in a sample including a plurality of patterns on a substantially same plane. A pattern measuring apparatus that scans a sample with charged particles, forms a detected image by detecting secondary charged particles or backscattered charged particles generated from the sample, and measures a pattern imaged on the detected image includes: an image acquiring section acquiring a plurality of detected images taken at a substantially same location on the sample under different imaging conditions; a contour extracting section extracting a plurality of pattern contours from the plurality of detected images; a contour reconstructing section reconstructing a contour to be measured by combining the plurality of pattern contours; and a contour measuring section making a measurement using the reconstructed contour to be measured.
    Type: Application
    Filed: May 21, 2013
    Publication date: December 5, 2013
    Inventors: Yoshinori Momonoi, Koichi Hamada, Yuji Takagi, Michio Hatano, Hideyuki Kazumi
  • Patent number: 8401273
    Abstract: A measurement tool apparatus for evaluating degradation of pattern features in a semiconductor device manufacturing process. The measurement tool apparatus detects variations in the patterns from SEM images thereof and extracts pattern edge points along the circumference of each pattern. The measurement tool apparatus compares the pattern edge points to corresponding edge points of an ideal shape so as to determine deviation of the patterns. Metrics are derived from analysis of the deviations. The measurement tool apparatus uses the metrics in calculating an index representative of the geometry of edge spokes of the pattern, an indicator of the orientation of the edge spokes, and/or anticipated effects of the edge spokes on device performance.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: March 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Momonoi, Atsuko Yamaguchi, Taro Osabe
  • Publication number: 20120098954
    Abstract: Provided are a semiconductor inspection device and a semiconductor inspection method such that in a specimen image in a single field of view obtained by an electron microscope, it is possible to suppress variations in the edge position measurement error attributable to the materials and structures of the lower layers of measured patterns by a first method, wherein the area in the field of view obtained by electron beam scanning is divided into a plurality of regions on the basis of information regarding the structures and materials of the object to be observed and the electron beam scanning conditions are changed for individual regions (805, 806), a second method, wherein, the image processing conditions are changed for individual regions resulting from division of the obtained images, or a third method, wherein the edge detection conditions are changed for individual regions resulting from the division within the edge inspection regions of the obtained images.
    Type: Application
    Filed: June 23, 2010
    Publication date: April 26, 2012
    Inventors: Atsuko Yamaguchi, Yoshinori Momonoi, Junichi Tanaka, Hiroki Kawada
  • Publication number: 20110176718
    Abstract: A measurement tool apparatus for evaluating degradation of pattern features in a semiconductor device manufacturing process. The measurement tool apparatus detects variations in the patterns from SEM images thereof and extracts pattern edge points along the circumference of each pattern. The measurement tool apparatus compares the pattern edge points to corresponding edge points of an ideal shape so as to determine deviation of the patterns. Metrics are derived from analysis of the deviations. The measurement tool apparatus uses the metrics in calculating an index representative of the geometry of edge spokes of the pattern, an indicator of the orientation of the edge spokes, and/or anticipated effects of the edge spokes on device performance.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Applicant: HITACHI, LTD.
    Inventors: Yoshinori MOMONOI, Atsuko YAMAGUCHI, Taro OSABE
  • Patent number: 6977229
    Abstract: The present invention is provided to prevent yield reduction of semiconductor device in dry cleaning of semiconductor device manufacturing process. The electric action and chemical action due to plasma of a first gas generated by means of a plasma generating means and the physical action due to viscous friction force of high speed gas flow generated by means of a planar pad that is brought close to the main surface of a wafer are applied together for cleaning the main surface of the wafer. After cleaning, the wafer is exposed to plasma of a second gas in the same vacuum chamber and then transferred to the atmosphere.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: December 20, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Masaru Izawa
  • Patent number: 6713401
    Abstract: Disclosed is a method for manufacturing a semiconductor device which efficiently carries out a process on a semiconductor substrate, such as dry etching, and cleaning for removing a foreign matter after the process. The method includes a step of removing a foreign matter by using both an electric action of a plasma generated by plasma generation means and a physical action caused by a frictional stress of a fast gas stream formed by a pad structure which is arranged close to a wafer surface.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Kazunori Tsujimoto, Shinichi Tachi
  • Publication number: 20040018727
    Abstract: The present invention is provided to prevent yield reduction of semiconductor device in dry cleaning of semiconductor device manufacturing process. The electric action and chemical action due to plasma of a first gas generated by means of a plasma generating means and the physical action due to viscous friction force of high speed gas flow generated by means of a planar pad that is brought close to the main surface of a wafer are applied together for cleaning the main surface of the wafer. After cleaning, the wafer is exposed to plasma of a second gas in the same vacuum chamber and then transferred to the atmosphere.
    Type: Application
    Filed: June 13, 2003
    Publication date: January 29, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Masaru Izawa
  • Patent number: 6643893
    Abstract: A dry cleaning device, wherein a pad is moved towards a surface of a wafer, cleaning gas is injected into a space formed between the pad and the wafer to generate a high-speed gas flow along the surface of the wafer whereby particles left on the surface of the wafer are removed with the high-speed gas flow. In addition, in order to assist this physical cleaning action, either a chemical or an electrical cleaning method such as a plasma additionally may be used.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 11, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Momonoi, Kenetsu Yokogawa, Masaru Izawa, Shinichi Tachi
  • Patent number: 6629538
    Abstract: A method of dry cleaning surfaces of a semiconductor wafer includes the steps of placing a processed wafer in a vacuum environment and positioning a pad near each of a front surface and a back surface of the wafer. Cleaning gas is injected into a small clearance formed between each pad and the front and rear surfaces to generate a high-speed gas flow along the surface of the wafer. Particles left at the surfaces of the processed wafer are physically cleaned and removed with the high-speed gas flow. In order to assist this physical cleaning action, it is also possible to apply either a chemical cleaning method or an electrical cleaning method under application of plasma.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: October 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Masaru Izawa, Shinichi Tachi
  • Patent number: 6551445
    Abstract: A parallel plate ECR plasma processing system is able to extend a plasma density region capable of keeping a continuous, uniform state. In this system, a first magnetic field-forming means formed of a solenoid coil and a second magnetic field-forming means are provided so that a the distribution of a direction of a magnetic line of flux on the surface of a planar plate is controlled by a combined magnetic field from the first and second magnetic field-forming means thereby controlling the distribution in degree of the interactions of the magnetic field and an electromagnetic wave. This control ensures the uniformity of a plasma under high density plasma formation conditions, thus enabling one to form a continuous plasma over a wide range of low to high densities. Thus, there can be realized a plasma processing system that ensures processing under wide plasma conditions including high-speed processing under high density conditions.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: April 22, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ken'etsu Yokogawa, Yoshinori Momonoi, Nobuyuki Negishi, Masaru Izawa, Shinichi Tachi
  • Patent number: 6475918
    Abstract: An etching method capable of obtaining a fine fabricated shape, particularly, a vertical fabricated shape with less bowing upon fabrication of insulation films in the production of semiconductors, the method comprising controlling the incident amount of O, F or N radicals, gas flow rate or consumption amount of O, F and N on the inner wall surface with etching time to suppress excessive O, F and N which become excessive in the initial stage of etching, the method also including control for the flow rate or the consumption amount based on the result of measurement for plasmas during etching so as to obtain a stable etching shape. Since bowing can be reduced upon fabrication of insulation film hole and insulation film while maintaining the etching rate and the selectivity, finer semiconductor device can be produced easily.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masaru Izawa, Kenetsu Yokogawa, Nobuyuki Negishi, Yoshinori Momonoi, Shinichi Tachi
  • Publication number: 20020094691
    Abstract: Disclosed is a method for manufacturing a semiconductor device which efficiently carries out a process on a semiconductor substrate, such as dry etching, and cleaning for removing a foreign matter after the process. The method includes a step of removing a foreign matter by using both an electric action of a plasma generated by plasma generation means and a physical action caused by a frictional stress of a fast gas stream formed by a pad structure which is arranged close to a wafer surface.
    Type: Application
    Filed: August 28, 2001
    Publication date: July 18, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Kazunori Tsujimoto, Shinichi Tachi
  • Publication number: 20020092541
    Abstract: There is disclosed a dry cleaning method capable of totally cleaning and removing particles left at the surfaces of the ultra fine structure of the semiconductor device within the vacuum state without being dependent on a wet cleaning method performed in the surrounding atmosphere. The dry cleaning method of the present invention is carried out such that each of the pads is approached to each of the front surface and the rear surface of a processed item such as the semiconductor wafer and the like, cleaning gas is injected into a fine clearance formed between both of them to generate a high-speed gas flow along the surface of the processed item and the particles left at the surfaces of the processed item are physically cleaned and removed with the high-speed gas flow. In order to assist this physical cleaning action, it is also possible to apply either a chemical cleaning method or an electrical cleaning method under application of plasma.
    Type: Application
    Filed: March 20, 2001
    Publication date: July 18, 2002
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Masaru Izawa, Shinichi Tachi
  • Publication number: 20020092121
    Abstract: There is disclosed a dry cleaning technology in which the particles left on the surface of the ultra-fine structure such as a semiconductor device and the like can be cleaned and removed totally in a vacuum environment without being dependent on a wet cleaning method performed in the surrounding atmosphere. In the dry cleaning device of the present invention, the pad is approached to the surface of the wafer such as a semiconductor wafer and the like, cleaning gas is injected into a fine clearance formed between both members to generate a high-speed gas flow along the surface of the wafer and the particles left on the surface of the wafer are physically cleaned and removed with the high-speed gas flow. In addition, in order to assist this physical cleaning action, either a chemical or an electrical cleaning method such as a plasma or the like can be used together.
    Type: Application
    Filed: March 16, 2001
    Publication date: July 18, 2002
    Inventors: Yoshinori Momonoi, Kenetsu Yokogawa, Masaru Izawa, Shinichi Tachi