Abstract: A current driver that can control variation in the consumed current in conjunction with variation in the setting value of the driving current. The mirror current of transistors Q2-0 to Q2-7 at each of output circuits 10-1 to 10-160 keeps flowing through output terminal To1 or node N8 irrespective of the setting value of the pixel data. Also, the mirror current of transistor Q4D keeps flowing in the series circuit of transistors Q4D and Q5D irrespective of the setting value of the pixel data. Consequently, even when the setting value of the driving current varies in various ways, the current consumed in each output circuit can still be kept constant. As a result, it is possible to prevent variation in the voltage of the power supply line in conjunction with variation of the consumed current, and it is possible to reduce fluctuation in the driving current between output channels.

Abstract: A pre-drive circuit having low deviation of timing of a high level and a low level output voltages is disclosed. A plurality of drive systems are comprised, each having an input amplifier circuits for amplifying input voltages input to input voltage terminals, high level shift circuits for shifting signal levels output from the input amplifier circuits, and output amplifier circuits for amplifying shift signals output from the high level shift circuits, and each drive system has the same constitution.

Abstract: In a driving method of a plasma display panel having a plurality of first electrodes provided so as to correspond to phosphors of a plurality of emitted light colors and having a plurality of second electrodes disposed so as to intersect with the first electrodes, the first electrodes for each of the emitted light colors that are provided so as to correspond to at least one of the phosphors of the emitted light colors among the first electrodes are brought into an electrically open state at the part of driving timings in a driving period. By doing so, gas discharge currents that flow through the first electrodes for each of the emitted light colors can be suppressed.

Abstract: A capacitive load driving circuit has an input terminal, a front-edge delay circuit, a back-edge delay circuit, an amplifying circuit, and an output switch device driven by the amplifying circuit. The front-edge delay circuit delays a front edge of an input signal input via the input terminal, the back-edge delay circuit delays a back edge of the input signal, and the amplifying circuit amplifies a drive control signal obtained through the front-edge delay circuit and the back-edge delay circuit.

Abstract: A drive circuit, for a display apparatus, capable of preventing the occurrence of malfunctions, when the power is turned on, and the destruction of an output device. The drive circuit comprises an edge pulse generation circuit for generating a front edge pulse and a back edge pulse of an input signal, a first level shift circuit for converting the front edge pulse, a second level shift circuit for converting the back edge pulse, a logic circuit, a flip-flop circuit, a setup resistor connected to a signal line in the flip-flop circuit or in the post stage of the flip-flop circuit, an output amplifier circuit connected to the post stage of the setup resistor, and an output device connected to the output amplifier circuit, wherein a capacitive load of the display apparatus is driven by the output device and the setup resistor is connected between the power supply signal line of the output amplifier circuit and the signal line.

Abstract: A semiconductor integrated circuit capable of reducing the influence of the difference in ambient temperature etc. and realizing a stable phase adjustment circuit has been disclosed. The semiconductor integrated circuit comprises a delay time adjustment circuit for delaying the rising edge or the falling edge of an input signal and changing the amount of delay, a comparison circuit for comparing an output signal from the delay time adjustment circuit with a predetermined voltage, a high-level shift circuit for shifting an output signal from the comparison circuit into a signal on the basis of an output reference voltage, and an output amplifier circuit for amplifying an output signal from the high-level shift circuit and outputting a signal for driving the semiconductor device, wherein the delay time adjustment circuit, the comparison circuit, the high-level shift circuit, and the output amplifier circuit are formed on a single chip.

Abstract: The present invention provides methods for treating or preventing neurodegenerative diseases such as amyotrophic lateral sclerosis (ALS), spinal muscular atrophy (SMA), Huntington's disease, Parkinson's disease, Alzheimer's disease, dementia after cerebral vascular disorder, dementia accompanied by other neuronal degeneration. The present invention provides methods for treating or preventing neurodegenerative diseases comprising administering a compound that upregulates neuronal apoptosis inhibitory protein (NAIP) production.

Abstract: A drive circuit module capable of dissipating heat produced by a semiconductor device, in the form of a bare chip, and in which the semiconductor device can be driven in a floating state, and a display device in which the drive circuit module is mounted have been disclosed. The drive circuit module comprises a heat dissipation plate, a flexible circuit board, an insulation layer having a wiring pattern, a semiconductor device mounting insulation layer, and a semiconductor device mounted on the heat dissipation plate via the semiconductor device mounting insulation layer, in which the insulation layer having the wiring pattern and the semiconductor device mounting insulation layer are made of a non-conductive resin, the flexible circuit board and the insulation layer having the wiring pattern are fixed on the heat dissipation plate directly or indirectly, and the semiconductor device is electrically connected to the wiring pattern and the flexible circuit board.

Abstract: A PDP apparatus in which a large-sized plasma display panel, whose electrodes have large drive requirements, is driven by using already existing driver ICs, and a PDP apparatus in which the operating conditions when a plasma display panel is driven by using a plurality of driver ICs have been improved, are disclosed. According to a first aspect, one electrode of the plasma display panel is driven by combining a plurality of drive signals output from the driver IC and, according to a second aspect, in a configuration in which a plurality of electrodes are driven by a plurality of identical driver ICs, when some of a plurality of outputs of the driver ICs are not connected to the electrodes and not used, the unused outputs are distributed in each driver IC as evenly as possible.

Abstract: A load drive circuit, successfully suppressed in unnecessary electromagnetic wave generation through suppressing transition time in the drive voltage waveform even under a reduced effective load, and a display device using this circuit are provided, wherein the circuit comprises a drive circuit inversively amplifying a signal, used for driving a load, input through an input terminal, and output from an output terminal; a first current source connected to the input terminal of the drive circuit and being capable of controlling current output; and a first switch circuit connected between the input terminal of the drive circuit and a first reference potential point.

Abstract: External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector transistor 34. When the voltage of external output terminal 28 can no longer be maintained by the first current supply circuit 11 alone as load 27 increases, clamping circuit 20 shuts off, and detector transistor 34 shuts off. As detector transistor 34 shuts off, the second current supplying element 12 becomes conductive and supplies a current to load 27. Because the second current supplying element 12 is not operating during normal operation during which the current consumption by load 27 is low, the current consumption is low. In addition, because no amplifier is required, only a small number of elements are required.

Abstract: A capacitive load driving circuit has an input terminal, a front-edge delay circuit, a back-edge delay circuit, an amplifying circuit, and an output switch device driven by the amplifying circuit. The front-edge delay circuit delays a front edge of an input signal input via the input terminal, the back-edge delay circuit delays a back edge of the input signal, and the amplifying circuit amplifies a drive control signal obtained through the front-edge delay circuit and the back-edge delay circuit.

Abstract: A pre-drive circuit having low deviation of timing of a high level and a low level output voltages is disclosed. A plurality of drive systems are comprised, each having an input amplifier circuits for amplifying input voltages input to input voltage terminals, high level shift circuits for shifting signal levels output from the input amplifier circuits, and output amplifier circuits for amplifying shift signals output from the high level shift circuits, and each drive system has the same constitution.

Abstract: A memory cell (10) is a so-called CMOS type cell. P-wells (W1P, W2P, W3P) and N-wells (W4N, W5N) are formed in a main surface (5S) of a semiconductor substrate (5), and the wells (W2P, W4N, W1P, W5N, W3P) are aligned in this order. Driver transistors (11DN, 12DN) are formed in the wells (W2P, W3P), respectively. Load transistors (11LP, 12LP) are formed in the wells (W4N, W5N), respectively. Two access transistors (11AN, 12AN) are formed in the single well (W1P). N+-type impurity regions (FN30, FN10) constituting one of storage nodes are provided in different wells, and N+-type impurity regions (FN31, FN11) constituting the other of the storage nodes are also provided in different wells.

Abstract: A memory cell (10) is a so-called CMOS type cell. P-wells (W1P, W2P, W3P) and N-wells (W4N, W5N) are formed in a main surface (5S) of a semiconductor substrate (5), and the wells (W2P, W4N, W1P, W5N, W3P) are aligned in this order. Driver transistors (11DN, 12DN) are formed in the wells (W2P, W3P), respectively. Load transistors (11LP, 12LP) are formed in the wells (W4N, W5N), respectively. Two access transistors (11AN, 12AN) are formed in the single well (W1P). N+-type impurity regions (FN30, FN10) constituting one of storage nodes are provided in different wells, and N+-type impurity regions (FN31, FN11) constituting the other of the storage nodes are also provided in different wells.

Abstract: A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed. A silicon oxide film, a polysilicon film and a silicon oxide film are formed in the order named on a silicon substrate. Then, the silicon oxide film is patterned to form silicon oxide films. Next, a photoresist is applied, and is then exposed to light using a photomask for defining the ends of gate structures as seen in a direction of a gate width. Next, the photoresist is developed to form openings. Using the photoresist as an etch mask, portions of the silicon oxide films exposed in the openings are etched away.

Abstract: An SRAM memory cell includes two inverters connected in complement with each other. Each inverter includes one NMOS transistor and one PMOS transistor. The gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. The drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. The drain of an another PMOS transistor and the gate of still another PMOS transistor are connected to the first node. The drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacitance and drain capacitance of these PMOS transistors is appended to the two nodes.

Abstract: The plasma display panel includes a pair of glass substrates forming therein display cells. One substrate has address electrodes and the other has sustain electrodes including X-electrodes and Y-electrodes. X-electrodes are connected to terminals of sustain pulse generating circuits provided on a printed circuit board, via intermediate circuit boards. The printed circuit board and the intermediate circuit boards are connected to each other by connectors having a first set of terminals connected to the first sustain pulse generating circuit and a second set of terminals connected to the second sustain pulse generating circuit. Terminals of first and second sets are arranged in a row alternately one by one, or group by group.

Abstract: External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector transistor 34. When the voltage of external output terminal 28 can no longer be maintained by the first current supply circuit 11 alone as load 27 increases, clamping circuit 20 shuts off, and detector transistor 34 shuts off. As detector transistor 34 shuts off, the second current supplying element 12 becomes conductive and supplies a current to load 27. Because the second current supplying element 12 is not operating during normal operation during which the current consumption by load 27 is low, the current consumption is low. In addition, because no amplifier is required, only a small number of elements are required.

Abstract: A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed is provided. A silicon oxide film (4), a polysilicon film (5) and a silicon oxide film (6) are formed in the order named on a silicon substrate (1). Then, the silicon oxide film (6) is patterned to form silicon oxide films (14a, 14b). Next, a photoresist (15) is applied, and is then exposed to light using a photomask (18) for defining the ends of gate structures (25i-25k) as seen in a direction of a gate width. Next, the photoresist (15) is developed to form openings (21s-21u). Using the photoresist (15) as an etch mask, portions of the silicon oxide films (14a, 14b) exposed in the openings (21s-21u) are etched away.