Abstract: An endoscope system includes an endoscope including a control section, an insertion section, and a light guide member, a light source configured to emit light guided by the light guide member, a failure-cause detecting circuit configured to detect a pre-failure state that causes a failure of the endoscope, and a light source controller configured to control an output of the light source based on a detection result of the failure-cause detecting circuit. The failure-cause detecting circuit includes a cause predicting circuit configured to detect a second pre-failure state in which it is predicted that the endoscope reaches a first pre-failure state that directly causes the failure of the endoscope. The light source controller controls the output of the light source based on a detection result of the cause predicting circuit.

Abstract: The present invention provides a nucleic acid which encodes an adeno-associated virus (AAV) capsid protein mutant that contains a peptide comprising an amino acid sequence selected from the group consisting of SEQ ID Nos. 15 to 62 or a peptide comprising an amino acid sequence produced by substituting, deleting, inserting and/or adding one or several amino acid residues in an amino acid sequence selected from the group consisting of SEQ ID Nos. 15 to 62; DNA comprising the nucleic acid; a cell harboring the DNA; and a method for producing the cell.

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

Abstract: A semiconductor laser device includes a semiconductor layer that includes a light emitting region having a first width and a pad region formed in a region outside the light emitting region and having a second width exceeding the first width, an insulating layer that covers the light emitting region and the pad region, and a wiring electrode that has an internal connection region penetrating through the insulating layer and electrically connected to the light emitting region and an external connection region that covers the pad region across the insulating layer and is to be externally connected to a lead wire.

Abstract: The disclosed technology is directed to a fixing unit of a light guide member. The fixing unit is attaching the light guide member to a protective member that protects outer circumference of the light guide member that guides primary light and a holding member. The fixing unit comprises a defining member forming a spatial region in which the protective member and the holding member are encapsulated separately from one another in a longitudinal axis direction of the fixing unit. An adhesive that is applied in the spatial region to bond at least part of the protective member and at least part of the holding member to the defining member. The defining member includes a specific region that defines a bonding range of the adhesive in the spatial region in at least one of a longitudinal axis direction and a radial direction of the defining member.

Abstract: The 3D sensing system includes: a PC laser array in which PC laser elements are arranged on a plane; a control unit configured to control an operation mode of a laser light source; a driving unit configured to execute a drive control of the PC laser array in accordance with an operation mode controlled by the control unit; a light receiving unit configured to receive reflected light that is laser light emitted from the PC laser array and reflected from a measuring object; a signal processing unit configured to execute signal processing of the reflected light received by the light receiving unit in accordance with the operation mode; and a distance calculation unit configure to execute calculation processing of a distance to the measuring object with respect to a signal processed by the signal processing unit, in accordance with the operation mode, and to output distance data.

Abstract: A method for manufacturing a surface emitting laser made of a group-III nitride semiconductor by an MOVPE method includes: (a) growing a first cladding layer of a first conductive type on a substrate; (b) growing a first optical guide layer of the first conductive type on the first cladding layer; (c) forming holes having a two-dimensional periodicity in a plane parallel to the first optical guide layer, in the first optical guide layer by etching; (d) supplying a gas containing a group-III material and a nitrogen source and performing growth to form recessed portions having a facet of a predetermined plane direction above openings of the holes, thereby closing the openings of the holes; and (e) planarizing the recessed portions by mass transport, after the openings of the holes have been closed, wherein after the planarizing at least one side surface of the holes is a {10-10} facet.

Abstract: There is provided an engine equipped with a supercharger that suppresses heat deterioration of engine oil. The engine equipped with a supercharger includes a supercharger; an oil supply passage that supplies engine oil to a shaft bearing part of the supercharger; an oil discharge passage that discharges the engine oil from the shaft bearing part of the supercharger; and a water-cooling-type oil cooler. The water-cooling-type oil cooler is provided in the oil discharge passage, and the engine oil discharged from the shaft bearing part of the supercharger is cooled by the engine cooling water that passes the water-cooling-type oil cooler. The engine cooling water is desirably supplied from the cylinder jacket to the water-cooling-type oil cooler.

Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region.

Abstract: A wireless communication system includes: a transmitting apparatus to transmit using one or more of radio resources; and a receiving apparatus to store correspondence information indicating a correspondence between a resource amount and a data size, the transmitting apparatus transmits to the receiving apparatus, data mapped to the radio resources, where the transmitting apparatus transmits a single control signal associated with the data to be transmitted across a plurality of time resource, the transmitting apparatus transmits a single control signal associated with the data transmitted across a plurality of frequency resources, the single control signal includes information indicating a value based on a number of the plurality of time resources, a number of the plurality of frequency resources, or information indicating a first resource amount wherein the receiving apparatus acquires a first data size being dependent on the value, the first resource amount, and correspondence information, and decode the da

Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region. The scanning antenna includes a TFT substrate, a slot substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, a seal portion provided in the non-transmission and/or reception region and surrounding the liquid crystal layer, and a reflective conductive plate disposed opposing a second main surface of a second dielectric substrate with a dielectric layer interposed between the reflective conductive plate and the second main surface. The slot electrode includes an opening or a recessed portion formed in the non-transmission and/or reception region and in the region surrounded by the seal portion.

Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region. The scanning antenna includes a TFT substrate, a slot substrate, a liquid crystal layer, a seal portion surrounding the liquid crystal layer, a wall structure (additional seal portion) disposed in a region surrounded by the seal portion in the non-transmission and/or reception region, a reflective conductive plate, a first spacer structure defining a first gap between a first dielectric substrate and a second dielectric substrate in the transmission and/or reception region, and a second spacer structure disposed in the wall structure and defining a second gap wider than the first gap.

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

Abstract: A wireless communications system configured to use a predetermined bandwidth of an unlicensed bandwidth, the wireless communications system including: a base station configured to transmit a control signal that includes information indicating an offset time from a reference timing; and a terminal connected to the base station and configured to: receive the control signal from the base station; perform a process of detecting a wireless signal of the predetermined bandwidth in a standard period; and start transmission from a transmission start timing according to the offset time after no wireless signal of the predetermined bandwidth is detected in the process, the transmission start timing being a timing at which the terminal is allowed to start transmission of wireless signals.

Abstract: A wireless communications system configured to perform wireless communication by using a first band dedicated to the system and a second band shared by the system and another wireless communications system, the system including: a base station configured to transmit in the first band to the terminal, a control signal permitting data transmission in the second band from a terminal to the base station; and the terminal configured to detect an available carrier wave of the second band after a predetermined time from the transmission of the control signal by the base station, the terminal performing the data transmission after waiting until detection of the available carrier wave.

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench ; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.

Abstract: A semiconductor circuit apparatus of the present disclosure includes a control circuit controlling a clock signal externally input, a drive circuit performing a switching operation according to a pulse signal provided by the control circuit, a series connection circuit including an inductor element, a switch element, and a capacitive element connected in series between a signal line and a fixed potential node, the series connection circuit forming an LC resonance circuit, and a level detection circuit having an input end connected to the signal line. An output from the level detection circuit is fed back to the control circuit.

Abstract: A surface emitting laser element formed of a group III nitride semiconductor, comprising: a first clad layer of a first conductivity type; a first guide layer of the first conductivity type having a photonic crystal layer formed on the first clad layer including voids disposed having two-dimensional periodicity in a surface parallel to the layer and a first embedding layer formed on the photonic crystal layer; a second embedding layer formed on the first embedding layer by crystal growth; an active layer formed on the second embedding layer; a second guide layer formed on the active layer; and a second clad layer of a second conductivity type formed on the second guide layer, the second conductivity type being a conductivity type opposite to the first conductivity type. The first embedding layer has a surface including pits disposed at surface positions corresponding to the voids.

Abstract: Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (?2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N?M?2) times the basic cell length which is appropriate to the single complementary transistor pair.