Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.

Abstract: A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits a plurality of data bits represented by whether the buses be driven to the master control unit in data transmission periods assigned to the slave control units based on a start of communication, and the master control unit drives the buses to insert a period for supplying power while data bits are being transmitted in the data transmission period. The slave control unit provides a non-driving period, which stops driving the buses, at an end of the data bit transmission period.

Abstract: A cutting point calculation step defines the cell complex that contains the boundary data, and calculating a cutting point where the boundary data cuts an edge or vertex of the rectangular parallelepiped cell of the cell complex. A cycle formation step classifies the rectangular parallelepiped cells into a boundary cell having the cutting point and a nonboundary cell having no cutting point, acquiring a cutting segment between a cell surface and boundary data for each boundary cell, and forming a cutting segment cycle closed by connecting the cutting points and the cutting segments alternately in sequence. A cycle internal division step divides the inside of the cutting segment cycle into cycle inner triangles sharing an adjacent side, for each boundary cell. A simplification step of unifying a plurality of cutting points on each edge, and registering the cycle inner triangles in the cell, for each boundary cell.

Abstract: A method and a program for converting boundary data into cell inner shape data, includes a division step (A) of dividing external data (12) constituted of the boundary data of an object into cells (13) in an orthogonal grid, a cutting point deciding step (B) of deciding an intersection point of the boundary data and a cell edge as a cell edge cutting point, a boundary deciding step (C) of deciding a boundary formed by connecting the cell edge cutting points as the cell inner shape data, a cell classification step (D) of classifying the divided cells into a nonboundary cell (13a) including no boundary surface and a boundary cell (13b) including a boundary surface, and a boundary cell data classification step (E) of classifying cell data constituting the boundary cell into internal cell data inside the cell inner shape data and external cell data outside the cell inner shape data.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.

Abstract: During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For motor control circuits that exist only in the target chip, the CPU accesses them via serial communication. When the one-chip microcomputer operates alone, its CPU switches a switching circuit to a JTAG interface side to actuate a motor control circuit via internal serial communication.

Abstract: A method of converting three-dimensional shape data into cell internal data. The method includes an oct-tree division step of dividing external data including boundary data of a target object into rectangular parallelepiped cells having boundary planes orthogonal to each other by oct-tree division. The method further includes a cell classification step of classifying each of the cells into an internal cell positioned inside or outside the target object or a boundary cell including the boundary data, and a cut point determination step of determining cut points of edges of the boundary cell based on the boundary data. The method further includes a boundary surface determination step of connecting cut points to form a polygon, and determining the polygon as the cell internal data when the number of the determined cut points is no fewer than 3 and no more than 12.

Abstract: There is disclosed a method comprising an external data entering step (A), a shape data dividing step (B) for dividing the external data into cubic shape cells 13 having boundary planes orthogonal to one another based on octree division, and storing shape data for each cell, and a physical quantity dividing step (C) for dividing a physical quantity of the object into different physical quantity cells 13? for each physical quantity based on octree division, and storing each physical quantity for each physical quantity cell. The shape cell 13 and each physical quantity cell 13? for each physical quantity are stored on different memory layers 18 in the same coordinate system, and managed in correlation with each other. In addition, the plurality of memory layers 18 are used singly or in combination for use of the data of the shape and the physical quantity.

Abstract: In a power supply circuit, when switches are turned off, current flows from a battery power supply line through resistors, input terminals, diodes and a terminal and further from a terminal into IC. When a microcomputer operates in a low power consumption operating mode, the power supply voltage is higher than a target voltage, and a control voltage output from an operational amplifier increases, so that a transistor is turned off. At this time, a current sink circuit operates and a transistor is turned on, so that excessive current flows into the current sink circuit to suppress increase of the power supply voltage.

Abstract: A signal output section of a port sampling circuit 6 periodically changes the output level of an output port 11 based on a sampling period stored in a register which is set by CPU 2. A data latch section of the port sampling circuit 6 latches the data given to an input port 10 based on a timing signal, with a starting point being set on a change point of the output level. A data register stores the latched data.

Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.

Abstract: A RISC type of CPU is provided to execute an object program in which a stack area is used. The CPU is configured to have a return instruction based on an operand at which an open size is specified and to perform the return instruction when the stack area is required to be opened in returning processing executed by the CPU from interrupt processing to ordinary processing with no interrupt. Also a compiler is provided to compile a source program into the object program. The compiler determines whether or not a stack area in the source program is required to be opened when processing in the source program is returned from interrupt processing to ordinary processing with no interrupt and produces codes of the object program in which an operand for a return instruction is included and an open size for the stack area is specified at the operand.

Abstract: A signal output section of a port sampling circuit 6 periodically changes the output level of an output port 11 based on a sampling period stored in a register which is set by CPU 2. A data latch section of the port sampling circuit 6 latches the data given to an input port 10 based on a timing signal, with a starting point being set on a change point of the output level. A data register stores the latched data.

Abstract: Disclosed is a single-chip microcomputer capable of facilitating debugging even in the case of including a plurality of CPUs. In the single-chip microcomputer 41 carrying two CPUs 41A and 41B, the CPU 42A is released from its reset condition by a power-on reset circuit 33 at power-on, while another CPU 42B is released from its reset condition through a CPU(B) reset register 44 in accordance with processing based on the control program of the CPU 42.

Abstract: A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a CPU identification register which stores an identification value for identifying the corresponding CPU. When a program which is specific to a CPU is to be executed by that CPU, the corresponding identification value is read out from the identification register of the CPU and is judged, and branching to the appropriate program is performed based on the judgement result.

Abstract: A single-chip microprocessor integrated circuit (IC) with a power saving function. The power saving function is achieved by address bus control and/or unique clock circuit. The invention is applicable to a single-chip microprocessor including a CPU; a CPU address bus; and a peripheral circuit comprising a plurality of circuit blocks connected with a peripheral address bus. All or a part of address data provided on the CPU address bus is passed to the peripheral address bus only if the address data is a peripheral address. The passed address is used for address decoding that involves switching. An inventive clock circuit provides each of the circuit blocks with one of predetermined clock signals according to clock control data given by the CPU.

Abstract: A selective output circuit of a DMA controller selectively outputs either an address change amount relevant to the transfer data size or an address change amount independent of the transfer data size to a second input port of an adder with reference to settings of control register. The adder has a first input port for receiving an address value being set in a source address register and a second input port for receiving the selected address change amount, and is arranged so as to output a summed-up result to the source address register.