Patents by Inventor Yoshio Sato

Yoshio Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4121424
    Abstract: At the point of time to when the turbine speed has come up to a first speed N.sub.1, a thermal stress expected in the turbine when the speed is increased to a second speed N.sub.2 at a rate .alpha..sub.1 is presumed. Thermal stress .sigma..sub.s(t) -.sigma..sub.sT1 at the point of time t.sub.o1 for commencing acceleration to the second speed N.sub.2 is then obtained, which point of time t.sub.o1 would never cause the maximum value of the presumed thermal stress to exceed a predetermined limit .sigma..sub.sl of the thermal stress when the turbine speed is increased at that rate. Then, a length of time T.sub.w1, referred to as a warming time, is determined which is required for the thermal stress .sigma..sub.s(t) to decrease to the level of (.sigma..sub.s(t) -.sigma..sub.sT1) when the warming is continued after the point of time t.sub.o. Subsequently, a length of time (N.sub.2 -N.sub.1)/.alpha..sub.1 required for increasing the turbine speed from N.sub.1 to N.sub.2 at the rate .alpha..sub.1 is calculated.
    Type: Grant
    Filed: February 15, 1977
    Date of Patent: October 24, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Sato, Mistuyo Nishikawa
  • Patent number: 4087627
    Abstract: A clock regenerator for a binary input which comprises a shift register having successively coupled first stages, a single predetermined stage, and second stages. A frequency divider device responsive to a local oscillation and with a controllable ratio produces timing pulses of a timing period equal to that prescribed number of clock periods which may be unity. Each timing pulse presets a binary signal in the single predetermined stage. The signal is shifted, when a transition occurs in binary values of the input signal within a predetermined interval defined by each timing period. The signal is shifted into the first and second stages if the transition occurs during a leading and a trailing half of each timing period, respectively, the timing pulse thus leading and lagging behind the input signal. The shifted binary signal controls the frequency division ratio to phase-synchronize the timing pulses with the input signal.
    Type: Grant
    Filed: October 12, 1976
    Date of Patent: May 2, 1978
    Assignees: Nippon Telegraph & Telephone Public Corporation, Nippon Electric Co., Ltd.
    Inventors: Yoshio Sato, Kazuhiro Ikeda