Patents by Inventor Yoshio Yokota

Yoshio Yokota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5376815
    Abstract: A semiconductor device having a bipolar MOS composite element pellet suitable for a compression structure. In this pellet, a semiconductor substrate on which a MOS composite element is formed is electrically connected to an external part by an electrode plate compressed to the substrate.
    Type: Grant
    Filed: September 21, 1993
    Date of Patent: December 27, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Yokota, Mitsuhiko Kitagawa, Dai Karasawa
  • Patent number: 5223442
    Abstract: Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: June 29, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Kitagawa, Yoshio Yokota, Kazuo Watanuki, Yoshinari Uetake, Kazunobu Nishitani, Tsuneo Ogura
  • Patent number: 5210601
    Abstract: According to this invention, a compression contacted semiconductor device is characterized by including a semiconductor pellet having main electrodes formed a first major surface of one surface side and a second major surface of another surface side, and electrode posts arranged on at least one major surface of the semiconductor pellet through an electrode member to sandwich the semiconductor pellet to compress the electrodes of the first and second major surfaces, wherein a crystal defect density is distributed within a surface of the semiconductor pellet so that a carrier lifetime of at least heat generating portions in the surface of the semiconductor pellet which do not sufficiently conduct heat to the electrode posts is shorter than a carrier lifetime of major heat generating portions which sufficiently conduct heat to the electrode posts. For this reason, current in the heat generating portions which do not sufficiently conduct heat to the electrode members is decreased.
    Type: Grant
    Filed: January 6, 1992
    Date of Patent: May 11, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Kitagawa, Yoshio Yokota, Kazuo Watanuki, deceased
  • Patent number: 5156981
    Abstract: Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.
    Type: Grant
    Filed: April 6, 1989
    Date of Patent: October 20, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiko Kitagawa, Yoshio Yokota, Kazuo Watanuki, Yoshinari Uetake, Kazunobu Nishitani, Tsuneo Ogura
  • Patent number: 5028974
    Abstract: A semiconductor switching device includes a high resistance first base layer of n-type formed on a first emitter layer of p-type through a low resistance buffer layer of n.sup.+ -type, second base layer of p-type formed on the first base layer, second emitter layers of n.sup.+ -type separately formed on the second base layer, anode and cathode main electrodes formed in contact with the first and second emitter layers, and a gate electrode formed in contact with the second base layer. Part of the low resistance buffer layer is exposed to the surface of the first emitter layer and is made contact with the anode main electrode to constitute a shorting portion. The width of the shorting portion is set smaller than one tenth of that of the second emitter layer in a longitudinal direction.
    Type: Grant
    Filed: February 5, 1990
    Date of Patent: July 2, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mituhiko Kitagawa, Tsuneo Ogura, Hiromichi Ohashi, Yoshinari Uetake, Yoshio Yokota, Kazuo Watanuki
  • Patent number: 4996586
    Abstract: A crimp-type semiconductor device having a non-alloy structure according to this invention has a silicon pellet including a plurality of cathode electrodes and a plurality of gate electrodes arranged to be alternately staggered with the cathode electrodes at the cathode side, and an anode electrode at the anode side. The cathode electrodes are crimped by a cathode electrode post via an electrode member constituted by a thin soft-metal plate and a hard metal plate. The anode electrode is crimped by an anode electrode post via an electrode member. Opposing surfaces of the electrodes, the electrode members, and the electrode posts are not bonded to but crimped in contact with each other. The electrode members are formed to cover the entire surfaces of the cathode electrode and the anode electrode, respectively, and the entire surface of the cathode electrode post and the anode electrode post, respectively.
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: February 26, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Matsuda, Takashi Fujiwara, Yoshio Yokota, Mitsuhiko Kitagawa, Masami Iwasaki, Kazuo Watanuki
  • Patent number: D459705
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: July 2, 2002
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Yoshio Yokota, Nobuyuki Yokote