Semiconductor package

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Description

FIG. 1 is a front, plan and right side perspective view of a semiconductor package showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a left side elevational view thereof; and,

FIG. 7 is a right side elevational view thereof.

The broken lines are shown in the views for illustrative purposes only and form no part of the claimed design.

Claims

The ornamental design for a semiconductor package, as shown and described.

Referenced Cited
U.S. Patent Documents
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D401567 November 24, 1998 Farnworth et al.
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Other references
  • Japanese Design Application No. 929231, Publication Date: Jul. 6, 1995.
  • Japanese Design Application No. 982886—Similar 1, Publication Date: Jun. 24, 1997.
  • Japanese Design Application No. 982886, Publication Date: Jun. 17, 1997.
Patent History
Patent number: D459705
Type: Grant
Filed: Jun 1, 2001
Date of Patent: Jul 2, 2002
Assignee: Shindengen Electric Manufacturing Co., Ltd. (Tokyo)
Inventors: Yoshio Yokota (Hanno), Nobuyuki Yokote (Hanno)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Antonelli, Terry, Stout & Kraus, LLP
Application Number: 29/142,698
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;