Patents by Inventor Yoshitaka Ishikawa
Yoshitaka Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953047Abstract: A formed body of Cu—Al—Mn-based shape-memory alloy may include a screw portion, wherein the screw portion is a form-rolled portion. A method for producing a formed body of Cu—Al—Mn-based shape-memory alloy may involve forming a screw portion having superelasticity by plastically working at least a portion of a material for the formed body with form-rolling in a state that a crystal structure is an A2-type structure and then, subjecting heat-treatment so as to convert the A2-type crystal structure into an L21-type crystal structure. The screw portion can be formed with good working property, and has excellent fatigue resistance and breaking resistance.Type: GrantFiled: January 27, 2020Date of Patent: April 9, 2024Assignee: FURUKAWA TECHNO MATERIAL CO., LTD.Inventors: Sumio Kise, Toyonobu Tanaka, Kenji Uruma, Kouji Ishikawa, Nanami Kataoka, Shigekazu Yokoyama, Toyohiko Higashida, Yoshitaka Azuma
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Publication number: 20230357954Abstract: A vapor phase growth apparatus of embodiments includes: a reactor; a holder provided in the reactor to place a substrate thereon; an annular out-heater provided below the holder; an in-heater provided below the out-heater; a disk-shaped upper reflector provided below the in-heater and formed of pyrolytic graphite; and a disk-shaped lower reflector provided below the upper reflector, formed of silicon carbide, and having a thickness smaller than that of the upper reflector.Type: ApplicationFiled: April 17, 2023Publication date: November 9, 2023Inventors: Masayuki TSUKUI, Yasushi IYECHIKA, Kiyotaka MIYANO, Yoshitaka ISHIKAWA
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Patent number: 11592340Abstract: A circuit device that is connected to a temperature detection element that detects a temperature of an object via an external signal line and an external signal ground line includes a connector that is connected to the external signal line and the external signal ground line, an internal signal line that is connected to the external signal line via the connector, an internal signal ground line that is connected to the external signal ground line via the connector, a controlling circuit that is connected to the internal signal line and the internal signal ground line and detects the temperature of the object, and a high-frequency filter that is inserted into at least one of a foremost stage of the internal signal line and a foremost stage of the internal signal ground line as viewed from the connector.Type: GrantFiled: July 23, 2018Date of Patent: February 28, 2023Assignees: SANYO Electric Co., Ltd., PANASONIC HOLDINGS CORPORATIONInventors: Shinya Nakano, Yoshitaka Ishikawa, Kenji Koizumi, Chikara Ohmori, Naohisa Morimoto
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Publication number: 20210126333Abstract: A circuit device that is connected to a temperature detection element that detects a temperature of an object via an external signal line and an external signal ground line includes a connector that is connected to the external signal line and the external signal ground line, an internal signal line that is connected to the external signal line via the connector, an internal signal ground line that is connected to the external signal ground line via the connector, a controlling circuit that is connected to the internal signal line and the internal signal ground line and detects the temperature of the object, and a high-frequency filter that is inserted into at least one of a foremost stage of the internal signal line and a foremost stage of the internal signal ground line as viewed from the connector.Type: ApplicationFiled: July 23, 2018Publication date: April 29, 2021Applicants: SANYO Electric Co., Ltd., Panasonic CorporationInventors: Shinya Nakano, Yoshitaka Ishikawa, Kenji Koizumi, Chikara Ohmori, Naohisa Morimoto
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Publication number: 20200115822Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber, a holder provided in the reaction chamber, the holder holding a substrate, a heater heating the substrate, a first reflector facing the holder, the heater being interposed between the first reflector and the holder, a second reflector provided between the first reflector and the heater, the second reflector having a compressive strength or a bending strength equal to or less than 1000 MPa or a Vickers hardness equal to or less than 8 GPa, the second reflector having a pattern, and a rotating shaft fixed to the holder, the rotating shaft rotating the holder.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Yoshitaka ISHIKAWA, Takehiko KOBAYASHI, Hideshi TAKAHASHI, Yasushi IYECHIKA, Takashi HARAGUCHI, Kiyotaka MIYANO
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Patent number: 10287707Abstract: A film growth apparatus according to one aspect of the present disclosure includes: a reactor configured to perform film growth processing on a substrate; an exhaust configured to discharge an exhaust gas from the reactor to the outside; a first valve including a valving element, the first valve provided in a pipe connecting the reactor with the exhaust and configured to control a pressure of the reactor by a position of the valving element; a valving element driver configured to cause the valving element to operate; and a valve controller including a closed position storage configured to store a closed position of the valving element, an opening degree controller configured to control the position of the valving element operated by the valving element driver, and a closed position shifter configured to detect a load of the valving element driver and shift the closed position in a case where the load exceeds a predetermined reference value.Type: GrantFiled: September 21, 2017Date of Patent: May 14, 2019Assignee: NuFlare Technology, Inc.Inventors: Yoshitaka Ishikawa, Hideshi Takahashi
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Patent number: 10204819Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber, a ring-shaped holder provided in the reaction chamber, the ring-shaped holder configured to hold a substrate, the ring-shaped holder including an outer portion having ring-shape and an inner portion having ring-shape, the inner portion including a substrate mounting surface positioned below an upper surface of the outer portion, the substrate mounting surface being a curved surface, the curved surface having convex regions and concave regions repeated in a circumferential direction, the curved surface having six-fold rotational symmetry, and a heater provided below the ring-shaped holder.Type: GrantFiled: October 20, 2017Date of Patent: February 12, 2019Assignee: NuFlare Technology, Inc.Inventors: Yasushi Iyechika, Masayuki Tsukui, Yoshitaka Ishikawa
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Patent number: 9972729Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.Type: GrantFiled: February 16, 2017Date of Patent: May 15, 2018Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
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Publication number: 20180114715Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber, a ring-shaped holder provided in the reaction chamber, the ring-shaped holder configured to hold a substrate, the ring-shaped holder including an outer portion having ring-shape and an inner portion having ring-shape, the inner portion including a substrate mounting surface positioned below an upper surface of the outer portion, the substrate mounting surface being a curved surface, the curved surface having convex regions and concave regions repeated in a circumferential direction, the curved surface having six-fold rotational symmetry, and a heater provided below the ring-shaped holder.Type: ApplicationFiled: October 20, 2017Publication date: April 26, 2018Inventors: Yasushi IYECHIKA, Masayuki TSUKUI, Yoshitaka ISHIKAWA
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Publication number: 20180087182Abstract: A film growth apparatus according to one aspect of the present disclosure includes: a reactor configured to perform film growth processing on a substrate; an exhaust configured to discharge an exhaust gas from the reactor to the outside; a first valve including a valving element, the first valve provided in a pipe connecting the reactor with the exhaust and configured to control a pressure of the reactor by a position of the valving element; a valving element driver configured to cause the valving element to operate; and a valve controller including a closed position storage configured to store a closed position of the valving element, an opening degree controller configured to control the position of the valving element operated by the valving element driver, and a closed position shifter configured to detect a load of the valving element driver and shift the closed position in a case where the load exceeds a predetermined reference value.Type: ApplicationFiled: September 21, 2017Publication date: March 29, 2018Inventors: Yoshitaka ISHIKAWA, Hideshi TAKAHASHI
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Publication number: 20180066381Abstract: A vapor phase growth apparatus according to an embodiment includes a reaction chamber, a holder provided in the reaction chamber, the holder holding a substrate, a heater heating the substrate, a first reflector facing the holder, the heater being interposed between the first reflector and the holder, a second reflector provided between the first reflector and the heater, the second reflector having a compressive strength or a bending strength equal to or less than 1000 MPa or a Vickers hardness equal to or less than 8 GPa, the second reflector having a pattern, and a rotating shaft fixed to the holder, the rotating shaft rotating the holder.Type: ApplicationFiled: September 1, 2017Publication date: March 8, 2018Inventors: Yoshitaka ISHIKAWA, Takehiko KOBAYASHI, Hideshi TAKAHASHI, Yasushi IYECHIKA, Takashi HARAGUCHI, Kiyotaka MIYANO
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Publication number: 20170162726Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Kazuhisa YAMAMURA, Akira SAKAMOTO, Terumasa NAGANO, Yoshitaka ISHIKAWA, Satoshi KAWAI
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Patent number: 9614109Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.Type: GrantFiled: April 10, 2015Date of Patent: April 4, 2017Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
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Patent number: 9385151Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.Type: GrantFiled: February 20, 2015Date of Patent: July 5, 2016Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
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Patent number: 9190551Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.Type: GrantFiled: February 15, 2010Date of Patent: November 17, 2015Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
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Publication number: 20150214395Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.Type: ApplicationFiled: April 10, 2015Publication date: July 30, 2015Inventors: Kazuhisa YAMAMURA, Akira SAKAMOTO, Terumasa NAGANO, Yoshitaka ISHIKAWA, Satoshi KAWAI
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Publication number: 20150171127Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regionsType: ApplicationFiled: February 20, 2015Publication date: June 18, 2015Inventors: Hiroshi OGURI, Yoshitaka ISHIKAWA, Akira SAKAMOTO, Tomoya TAGUCHI, Yoshimaro FUJII
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Patent number: 8994135Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.Type: GrantFiled: December 23, 2013Date of Patent: March 31, 2015Assignee: Hamamatsu Photonics K.K.Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
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Patent number: 8993361Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions.Type: GrantFiled: August 28, 2013Date of Patent: March 31, 2015Assignee: Hamamatsu Photonics K.K.Inventors: Hiroshi Oguri, Yoshitaka Ishikawa, Akira Sakamoto, Tomoya Taguchi, Yoshimaro Fujii
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Patent number: 8742528Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.Type: GrantFiled: February 15, 2010Date of Patent: June 3, 2014Assignee: Hamamatsu Photonics K.K.Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai