Patents by Inventor Yoshitaka Ishikawa

Yoshitaka Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140110808
    Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
    Type: Application
    Filed: December 23, 2013
    Publication date: April 24, 2014
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuhisa YAMAMURA, Akira SAKAMOTO, Terumasa NAGANO, Yoshitaka ISHIKAWA, Satoshi KAWAI
  • Publication number: 20140061840
    Abstract: A manufacturing method for an edge illuminated type photodiode has: a process of forming an impurity-doped layer of a first conductivity type in each of device forming regions in a semiconductor substrate; a process of forming an impurity-doped layer of a second conductivity type in each of the device forming regions; a process of forming a trench extending in a direction of thickness of the semiconductor substrate from a principal surface, at a position of a boundary between adjacent device forming regions, by etching to expose side faces of the device forming regions; a process of forming an insulating film on the exposed side faces of the device forming regions; a process of forming an electrode for each corresponding impurity-doped layer on the principal surface side of the semiconductor substrate; and a process of implementing singulation of the semiconductor substrate into the individual device forming regions
    Type: Application
    Filed: August 28, 2013
    Publication date: March 6, 2014
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroshi OGURI, Yoshitaka ISHIKAWA, Akira SAKAMOTO, Tomoya TAGUCHI, Yoshimaro FUJII
  • Publication number: 20120061785
    Abstract: A photodiode PD1 is provided with an n? type semiconductor substrate 1 with a pn junction formed of a first conductivity type semiconductor region and a second conductivity type semiconductor region. For the n? type semiconductor substrate 1, an accumulation layer 7 is formed on the second principal surface 1b side of the n? type semiconductor substrate 1 and an irregular asperity 10 is formed at least in regions opposed to the pn junction in a first principal surface 1a and in the second principal surface 1b. The regions opposed to the pn junction in the first principal surface 1a and in the second principal surface 1b of the n? type semiconductor substrate 1 are optically exposed.
    Type: Application
    Filed: June 2, 2010
    Publication date: March 15, 2012
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshitaka Ishikawa, Akira Sakamoto, Kazuhisa Yamamura, Satoshi Kawai
  • Publication number: 20110298076
    Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
    Type: Application
    Filed: February 15, 2010
    Publication date: December 8, 2011
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
  • Publication number: 20110291218
    Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CR The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.
    Type: Application
    Filed: February 15, 2010
    Publication date: December 1, 2011
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
  • Publication number: 20090121306
    Abstract: The present invention provides a photodiode array which can secure a sufficient aperture ratio with respect to light to be detected while restraining crosstalk between photodetecting channels even during operation in Geiger mode. In a photodiode array 1, resistors 42 and wirings 43 to be electrically connected to avalanche multipliers 6, respectively, are collectively formed on the upper surface side of a semiconductor substrate 2. Therefore, by setting the lower surface side of the semiconductor substrate 2 as a light-incident side, a sufficient aperture ratio can be secured while restraining crosstalk between photodetecting channels 10 by separators 5. Furthermore, on the lower surface side of the semiconductor substrate 2, accumulation layers 7 are formed, so that high quantum efficiency in each photodetecting channel 10 is secured and the effective aperture ratio is improved.
    Type: Application
    Filed: December 21, 2005
    Publication date: May 14, 2009
    Inventor: Yoshitaka Ishikawa
  • Patent number: 5843204
    Abstract: In a method of recycling iron and steel industry waste by processing the waste as an object substance by the use of a rotary kiln, the object substance is changed into a valuable material while the object substance travels within the rotary kiln from an upstream side to a downstream side. The object substance is heated on the upstream side of the rotary kiln within a reducing atmosphere to be reduced and molten into a reduced and molten product. The reduced and molten product is quickly sent to the downstream side without being adhered to an internal wall of the rotary kiln. The valuable material is extracted from the reduced and molten product which may be directly discharged out of the rotary kiln or which may be discharged after the reduced and molten product is once kept in a basin formed in the vicinity of the downstream side of the rotary kiln.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: December 1, 1998
    Assignees: Sumitomo Heavy Industries, Ltd., Sumitomo Metal Industries, Ltd.
    Inventors: Yoshitaka Ishikawa, Susumu Ide, Toshio Matsuoka, Shinichi Kurozu, Hiroshi Koide, Shigeru Morishita, Tateki Mori
  • Patent number: 5654536
    Abstract: In a photomultiplier of the present invention, a semiconductor device arranged in an envelope to oppose a photocathode is constituted by a semiconductor substrate of a first conductivity type, a carrier multiplication layer of a second conductivity type different from the first conductivity type, which is formed on the semiconductor substrate by opitaxial growth, a breakdown voltage control layer of the second conductivity type, which is formed on the carrier multiplication layer and has a dopant concentration higher than that of the carrier multiplication layer, a first insulating layer formed on the breakdown voltage control layer and said carrier multiplication layer while partially exposing the surface of the breakdown voltage control layer as a receptor for photoelectrons and consisting of a nitride, and an ohmic electrode layer formed on a peripheral surface portion of the receptor of the breakdown voltage control layer.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: August 5, 1997
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Motohiro Suyama, Masaharu Muramatsu, Makoto Oishi, Yoshitaka Ishikawa, Koei Yamamoto
  • Patent number: 4805695
    Abstract: Counterflow heat exchanger with a floating plate, which comprises a casing made of a pair of rectangular parallel-spaced wall members and four pieces of bar members connecting the corresponding corners of the pair of wall members, a pair of seal strips located inside said bar members through elastic members diagonally with regard to a line connecting the centers of the wall members, being extended so as to cover and seal a pair of the sides formed by a longer side of the wall members and the bar members, leaving a part of the sides uncovered. More than two sheets of floating plates are spaced apart from each other contained in a space formed by the seal strips and wall members. A spacer in a channel is formed between the floating plates, and a structure for controlling the flow of fluids within the channels is included. By making fluids having different temperatures flow countercurrently to each other through the channels, efficiency of heat exchange of the heat exchanger can be improved.
    Type: Grant
    Filed: December 23, 1987
    Date of Patent: February 21, 1989
    Assignee: Sumitomo Heavy Industries, Ltd.
    Inventors: Yoshitaka Ishikawa, Takeo Matsumoto
  • Patent number: 3943583
    Abstract: A bed provided with a commode or stool has a main mattress provided with a through-hole into which the commode or an auxiliary mattress may be positioned alternately by manipulation of an operating panel mounted at or near the bed. The front part of the main mattress may be erected along a transverse fold line so as to serve as reclining portion.
    Type: Grant
    Filed: November 26, 1974
    Date of Patent: March 16, 1976
    Assignee: Daika Kabushiki-Kaisha
    Inventor: Yoshitaka Ishikawa