Patents by Inventor Yoshitaka Kimura

Yoshitaka Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120044405
    Abstract: An autofocus system is provided that includes a focus-verification image-recapturing processor and a focus-verification image display processor. The focus-verification image-recapturing processor sets ISO sensitivity to a value lower than a predetermined value and increases an exposure value by adjusting at least one of an aperture value and an exposure time to carry out a focus-verification image-recapturing operation under focusing conditions applied in an antecedent autofocus operation when ISO sensitivity that is set in said auto focus operation exceeds the predetermined value. The focus-verification image display processor displays a focus-verification image obtained by the focus-verification image-recapturing operation when the ISO sensitivity that is set in the auto focus operation exceeds the predetermined value.
    Type: Application
    Filed: June 9, 2011
    Publication date: February 23, 2012
    Applicant: HOYA CORPORATION
    Inventors: Yoshitaka KIMURA, Hiroyuki TANAKA
  • Patent number: 8116857
    Abstract: There is provided a non-linear signal separation method using the non-linear state space projection method capable of separating an effective non-linear signal even if the S/N ratio is low by performing the time domain high speed non-linear state space projection when a signal is a multi-channel signal and has a periodicity. In the non-linear signal separation method using the non-linear state space projection method, an original signal having a complex signal which is a multi-channel and cyclic signal measured from one phenomenon is processed by using the time domain high-speed non-linear state space projection method so as to estimate a noise in the original signal and subtract the estimated noise from the original signal, thereby separating the signal to be measured in the original signal as a non-linear signal even when the S/N ratio is low.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: February 14, 2012
    Assignee: Tohoku University
    Inventors: Yoshitaka Kimura, Shinichi Chida, Mitsuyuki Nakao, Kunihiro Okamura, Takuya Ito
  • Publication number: 20120009626
    Abstract: A hydrothermal decomposition apparatus 17 as a biomass processing apparatus that decomposes a biomass material 11 into cellulose, hemicellulose, and lignin under a high temperature and high pressure condition to remove a lignin component and a hemicellulose component, a biomass solid discharging unit 18 that discharges a biomass solid (a hot-water insoluble component) 20 processed in the hydrothermal decomposition apparatus 17, and a slurrying vessel 21 communicating with the biomass solid discharging unit 18, into which water 19 is injected and the discharged biomass solid 20 is added to make it slurried are provided to an apparatus body 13, which is a processing vessel having a gas-liquid interface 13a.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hideo Suzuki, Yoshio Kuromi, Yoshitaka Kimura
  • Publication number: 20120009642
    Abstract: A biomass hydrothermal decomposition system includes a hydrothermal decomposition unit 17 that transports the fed biomass material from a lower side to an upper side in an apparatus body 13 by screw means 14, feeds pressurized hot water 15 from an upper side different from a feed position of the biomass material 11 into the apparatus body 13, which is pressurized hot water to be discharged, so as to separate a lignin component and a hemicellulose component from the biomass material; a biomass solid discharging unit 18 that discharges a biomass solid 20 from the upper side of the apparatus body 13; and a slurrying vessel 21 communicating with the biomass solid discharging unit 18, into which water 19 is injected and the discharged biomass solid 20 is added to obtain a slurried biomass solid are provided.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hideo Suzuki, Yoshio Kuromi, Yoshitaka Kimura
  • Patent number: 7997939
    Abstract: A plug includes a plug housing and a metal terminal group. The metal terminal group includes a mating electrode group on the first end side thereof and a connection electrode group on the second end side, the mating electrode group including mating electrode sections that are disposed with an insulating resin interposed therebetween and are to be in contact with the contacts of a mating jack, the connection electrode group including connection electrode sections that are disposed with an insulating resin interposed therebetween and are connected to the electrodes of a connection member. The mating electrode sections are disposed coaxially with an axis P of the plug, and at least two of the connection electrode sections are disposed around the axis P so as to surround the axis P side by side.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: August 16, 2011
    Assignee: SMK Corporation
    Inventors: Taku Akaiwa, Susumu Shinozaki, Takeshi Matsuda, Tatsuo Kato, Masaji Komuro, Kenji Nakazawa, Kenji Hatano, Yoshitaka Kimura
  • Publication number: 20110183277
    Abstract: A solenoid valve driving apparatus includes switching means for ON/OFF-controlling application of a direct current voltage to a solenoid of a solenoid valve, and signal outputting means. A first period and a consecutive second period are set as a valve opening operation period of the solenoid valve. When the signal outputting means outputs the PWM signal to the switching means, a duty ratio of the output signal is set to be higher in the second period than in the first period so that a power supplied to the solenoid is larger in the second period than in the first period. As a result, a valve opening operation is performed in the solenoid valve reliably, and loud noise generation during the valve opening operation is suppressed.
    Type: Application
    Filed: January 27, 2011
    Publication date: July 28, 2011
    Applicant: NORITZ CORPORATION
    Inventors: Daisuke Konishi, Akira Ohta, Yoshihisa Kitano, Tomoya Nakano, Yoshifumi Atobe, Haruki Inoue, Yoshitaka Kimura, Ryo Ikeda, Tomoki Kishimoto, Yasuhide Ikeuchi, Tomoko Ikeuchi
  • Publication number: 20110136392
    Abstract: A plug includes a plug housing and a metal terminal group. The metal terminal group includes a mating electrode group on the first end side thereof and a connection electrode group on the second end side, the mating electrode group including mating electrode sections that are disposed with an insulating resin interposed therebetween and are to be in contact with the contacts of a mating jack, the connection electrode group including connection electrode sections that are disposed with an insulating resin interposed therebetween and are connected to the electrodes of a connection member. The mating electrode sections are disposed coaxially with an axis P of the plug, and at least two of the connection electrode sections are disposed around the axis P so as to surround the axis P side by side.
    Type: Application
    Filed: July 28, 2010
    Publication date: June 9, 2011
    Applicant: SMK CORPORATION
    Inventors: Taku AKAIWA, Susumu SHINOZAKI, Takeshi MATSUDA, Tatsuo KATO, Masaji KOMURO, Kenji NAKAZAWA, Kenji HATANO, Yoshitaka KIMURA
  • Patent number: 7958481
    Abstract: An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: June 7, 2011
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Yoshitaka Kimura
  • Publication number: 20100200126
    Abstract: The present invention provides a production facility of hot dip galvannealed steel plate able to produce hot dip galvannealed steel plate on production conditions optimal at all times despite rapid changes in the steel type, plating deposition, and other external factors, wherein the production facility 1 of hot dip galvannealed steel plate is provided with a soaking/cooling furnace 7 for treating steel plate I running after leaving a rapid heating furnace 6 by at least one of soaking and cooling. Further, the soaking/cooling furnace 7 is configured to enable a change of the ratio in the furnace of the soaking region 15 for soaking steel plate I by soaking means 21 at a soaking temperature of 500° C. to 650° C. and the cooling region 16 for cooling the steel plate I by spray nozzles 22 by a 5° C./sec or more average cooling rate.
    Type: Application
    Filed: October 3, 2007
    Publication date: August 12, 2010
    Inventors: Hajime Onozawa, Yoshitaka Kimura
  • Publication number: 20100076330
    Abstract: Disclosed are a fetus electrocardiogram signal measuring method and its device that are capable of measuring the electrocardiogram signals of a fetus even during fetus movements and even at a gestational age during which the measurement current is weak, without the need for reattaching the electrodes and providing any shield room, even if the mother is a hospitalized or ambulant pregnant woman. The fetus electrocardiogram signal measuring device includes (1) high input impedance electrodes, (2) region-variable ground electrodes, and (3) a differential amplifier circuit and an optimization computing section.
    Type: Application
    Filed: January 22, 2008
    Publication date: March 25, 2010
    Applicant: TOHOKU TECHNO ARCH CO., LTD.
    Inventors: Yoshitaka Kimura, Mitsuyuki Nakao, Takuya Ito, Kazunari Ohwada
  • Patent number: 7659629
    Abstract: A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: February 9, 2010
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Yoshitaka Kimura
  • Publication number: 20090270713
    Abstract: There is provided a non-linear signal separation method using the non-linear state space projection method capable of separating an effective non-linear signal even if the S/N ratio is low by performing the time domain high speed non-linear state space projection when a signal is a multi-channel signal and has a periodicity. In the non-linear signal separation method using the non-linear state space projection method, an original signal having a complex signal which is a multi-channel and cyclic signal measured from one phenomenon is processed by using the time domain high-speed non-linear state space projection method so as to estimate a noise in the original signal and subtract the estimated noise from the original signal, thereby separating the signal to be measured in the original signal as a non-linear signal even when the S/N ratio is low.
    Type: Application
    Filed: August 22, 2006
    Publication date: October 29, 2009
    Applicant: TOHOKU UNIVERSITY
    Inventors: Yoshitaka Kimura, Shinichi Chida, Mitsuyuki Nakao, Kunihiro Okamura, Takuya Ito
  • Publication number: 20090064078
    Abstract: An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit region includes a plurality of circuit patterns, which form circuit elements of the semiconductor integrated circuit, in a plurality of pattern layers. The dummy region includes a plurality of character dummies, which do not contribute to an operation of the semiconductor integrated circuit. The character dummies have a fixed shape and dimension, and arranged in a character pattern layer selected from the plurality of pattern layers with a fixed pitch. The dummy region further includes an identification sign formed by connecting selected ones of the character dummies chosen from the plurality of the character dummies.
    Type: Application
    Filed: August 27, 2008
    Publication date: March 5, 2009
    Applicant: KAWASAKI MICROELECTRONICS, INC.
    Inventor: Yoshitaka Kimura
  • Publication number: 20080146953
    Abstract: [PROBLEMS] An electrocardiogram signal processing method for extracting a fetus electrocardiogram signal included in a biopotential signal detected from an electrode attached to a mother's body.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 19, 2008
    Inventors: Yoshitaka Kimura, Mitsuyuki Nakao, Shinichi Chida, Kunihiro Okamura, Michiyoshi Sato, Takuya Ito, Takayuki Shimazaki, Junichi Sugawara, Masato Senoo
  • Patent number: 7301797
    Abstract: A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: November 27, 2007
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Yoshitaka Kimura
  • Publication number: 20070102820
    Abstract: A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 10, 2007
    Applicant: KAWASAKI MICROELECTRONICS, INC.
    Inventor: Yoshitaka Kimura
  • Patent number: 7160786
    Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: January 9, 2007
    Assignee: Kawaski Microelectronics, Inc.
    Inventor: Yoshitaka Kimura
  • Publication number: 20050213371
    Abstract: A method of operating a semiconductor integrated circuit including a SRAM block, in which non-volatile data is stored in the SRAM block, is disclosed. In an exemplary embodiment, the non-volatile data is stored by flowing a drain current in one of a pair of pull-down transistors constituting the SRAM cell while supplying a fixed potential to the sources of the pull-down transistors. A semiconductor integrated circuit including a SRAM block and a control circuit that controls the SRAM block to store non-volatile data is also disclosed.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 29, 2005
    Applicant: KAWASAKI MICROELECTRONICS, INC.
    Inventor: Yoshitaka Kimura
  • Publication number: 20050059202
    Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOl substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.
    Type: Application
    Filed: October 4, 2004
    Publication date: March 17, 2005
    Applicant: Kawasaki Microelectronics, Inc.
    Inventor: Yoshitaka Kimura
  • Publication number: 20050042806
    Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.
    Type: Application
    Filed: October 4, 2004
    Publication date: February 24, 2005
    Applicant: Kawasaki Microelectronics, Inc.
    Inventor: Yoshitaka Kimura