Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: A semiconductor memory device comprises a semiconductor substrate comprising a first region, a second region, and a third region provided therebetween. The first region comprises: first conductive layers; a first semiconductor layer facing the first conductive layers; and a second semiconductor layer connected to the first semiconductor layer. The second region comprises: a third semiconductor layer and fourth semiconductor layer; and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The third region comprises a fifth semiconductor layer and sixth semiconductor layer that are formed continuously with the second semiconductor layer and the third semiconductor layer or fourth semiconductor layer, and extend in a second direction. The third region comprises first and second portions aligned alternately in the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: A semiconductor memory device comprises a semiconductor substrate comprising a first region, a second region, and a third region provided therebetween. The first region comprises: first conductive layers; a first semiconductor layer facing the first conductive layers; and a second semiconductor layer connected to the first semiconductor layer. The second region comprises: a third semiconductor layer and fourth semiconductor layer; and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The third region comprises a fifth semiconductor layer and sixth semiconductor layer that are formed continuously with the second semiconductor layer and the third semiconductor layer or fourth semiconductor layer, and extend in a second direction. The third region comprises first and second portions aligned alternately in the second direction.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: A clutch disc assembly includes a hub flange, an output hub, an intermediate hub, a plurality of first elastic members, and a plurality of second elastic members. Power from an engine is input into the hub flange. The output hub can be coupled to an input shaft of the transmission. The intermediate hub is arranged between the hub flange and the output hub in a diameter direction such that relative rotation with the hub flange by an angle greater than or equal to a first angular range is prevented, and such that relative rotation with the output hub by an angle greater than or equal to a second angular range is prevented. The plurality of first elastic members couple the hub flange and the intermediate hub elastically in a rotation direction. The plurality of second elastic members couple the intermediate hub and the output hub elastically in the rotation direction.

Abstract: An algae treatment method includes: a first step of culturing microalgae in a culture medium having an initial nitrogen concentration of less than 12 mg/L for three days or more; and a second step of performing a thermal treatment of the microalgae that has gone through the first step at a pH of 2.0 or more and 10.0 or less and a temperature of 35° C. or more and 80° C. or less.

Abstract: A damper disc assembly includes an input plate, an output unit including an input-side member and an output-side member, a high stiffness damper unit, a low stiffness damper unit and first and second hysteresis torque generating mechanisms. The low stiffness damper unit is disposed axially between the input plate and the input-side member, and is actuated in a low torsion angular range of torsional characteristics. The first hysteresis torque generating mechanism generates a first hysteresis torque in a lower torsion angular part of an actuation range of the low stiffness damper unit. The second hysteresis torque generating mechanism generates a second hysteresis torque in a higher torsion angular part of the actuation range of the low stiffness damper unit and an actuation range of the high stiffness damper unit.

Abstract: A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first insulation material. A memory pillar extends through the first conductive layers. A hookup region is adjacent to the memory block and includes conductive layers stacked on the substrate at levels from the substrate that corresponds to the conductive layers in the memory block. An isolation region is between the memory block and the hookup region and includes first insulating layers of a second insulating material different than the first insulating material. Each first insulating layer is at a level from the substrate that corresponds to one of the first conductive layers and each first insulating layer is between one of the conductive layers in the memory block and one of the conductive layers in hookup region.

Abstract: A clutch disc assembly includes a hub flange, an output hub, an intermediate hub, a plurality of first elastic members, and a plurality of second elastic members. Power from an engine is input into the hub flange. The output hub can be coupled to an input shaft of the transmission. The intermediate hub is arranged between the hub flange and the output hub in a diameter direction such that relative rotation with the hub flange by an angle greater than or equal to a first angular range is prevented, and such that relative rotation with the output hub by an angle greater than or equal to a second angular range is prevented. The plurality of first elastic members couple the hub flange and the intermediate hub elastically in a rotation direction. The plurality of second elastic members couple the intermediate hub and the output hub elastically in the rotation direction.

Abstract: A damper disc assembly includes first and second input plates, an output unit, a high stiffness damper unit, and first and second low stiffness damper units. The output unit includes an input-side member and an output-side member disposed rotatably relative to each other. The high stiffness damper unit elastically couples the input-side member and the first and second input plates in a rotational direction and is actuated in a high torsion angular range of torsional characteristics. The first and second low stiffness damper units elastically couple the input-side member and the output-side member and are actuated in a low torsion angular range of the torsional characteristics. The second low stiffness damper unit is actuated later than actuation of the first low stiffness damper unit.

Abstract: A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first insulation material. A memory pillar extends through the first conductive layers. A hookup region is adjacent to the memory block and includes conductive layers stacked on the substrate at levels from the substrate that corresponds to the conductive layers in the memory block. An isolation region is between the memory block and the hookup region and includes first insulating layers of a second insulating material different than the first insulating material. Each first insulating layer is at a level from the substrate that corresponds to one of the first conductive layers and each first insulating layer is between one of the conductive layers in the memory block and one of the conductive layers in hookup region.

Abstract: A damper disc assembly includes an input plate, an output unit including an input-side member and an output-side member, a high stiffness damper unit, a low stiffness damper unit and first and second hysteresis torque generating mechanisms. The low stiffness damper unit is disposed axially between the input plate and the input-side member, and is actuated in a low torsion angular range of torsional characteristics. The first hysteresis torque generating mechanism generates a first hysteresis torque in a lower torsion angular part of an actuation range of the low stiffness damper unit. The second hysteresis torque generating mechanism generates a second hysteresis torque in a higher torsion angular part of the actuation range of the low stiffness damper unit and an actuation range of the high stiffness damper unit.

Abstract: A damper disc assembly includes first and second input plates, an output unit, a high stiffness damper unit, and first and second low stiffness damper units. The output unit includes an input-side member and an output-side member disposed rotatably relative to each other. The high stiffness damper unit elastically couples the input-side member and the first and second input plates in a rotational direction and is actuated in a high torsion angular range of torsional characteristics. The first and second low stiffness damper units elastically couple the input-side member and the output-side member and are actuated in a low torsion angular range of the torsional characteristics. The second low stiffness damper unit is actuated later than actuation of the first low stiffness damper unit.

Abstract: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.