Patents by Inventor Yoshitaka Nakamura
Yoshitaka Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240098969Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three-dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by single crystalline silicon (Si) channel regions. The single crystalline silicon (Si) channel regions can include a dielectric material to provide support structure to the single crystalline channel regions when forming the horizontal access devices in vertical three-dimensional (3D) memory. Horizontally oriented access lines can connect to gate structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: David K. Hwang, Yoshitaka Nakamura, Scott E. Sills, Si-Woo Lee, Yuanzhi Ma, Glen H. Walters
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Publication number: 20240098970Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by silicon (Si) channel regions. A digit line having a global digit line (GDL) contact is formed in a trench adjacent to the first source/drain regions. In one example, the digit line is electrically isolated from a neighboring digit line at the bottom of the trench. In another example, the digit line is formed continuously along a bottom surface of trench to form shared digit lines between horizontal access devices, in two separate arrays, on opposing second vertical surfaces. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Scott E. Sills, Si-Woo Lee, David K. Hwang, Yoshitaka Nakamura, Yuanzhi Ma, Glen H. Walters
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Patent number: 11932263Abstract: A travel sickness estimation system includes an estimation unit and an output unit. The estimation unit is configured to perform estimation processing of estimating, based on person information indicating conditions of a person who is on board a moving vehicle, whether or not the person is in circumstances that would cause travel sickness for him or her. The output unit is configured to output a result of the estimation processing performed by the estimation unit.Type: GrantFiled: March 13, 2019Date of Patent: March 19, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuta Moriura, Yoshitaka Nakamura, Yasufumi Kawai, Hiroyuki Handa, Yohei Morishita, Toru Okino, Hiroyuki Hagino, Toru Sakuragawa, Satoshi Morishita
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Patent number: 11927646Abstract: Provided is a magnetic field measuring apparatus, comprising: a magnetic sensor array including a plurality of magnetic sensor cells, which is capable of detecting an input magnetic field in three axial directions at a plurality of locations in three-dimensional space; a measurement data acquiring section for acquiring measurement data based on the input magnetic field including a to-be-measured magnetic field; and a measurement data computing section for calibrating the measurement data acquired by the measurement data acquiring section; wherein the measurement data computing section comprises: an indicator calculation section for calculating an indicator illustrating calibration accuracy of the measurement data computing section; and a failure determination section for determining a failure based on the indicator calculated by the indicator calculation section; wherein each of the plurality of magnetic sensor cells comprises: a magnetic sensor; and an output section for outputting a output signal.Type: GrantFiled: May 25, 2021Date of Patent: March 12, 2024Assignee: Asahi Kasei Microdevices CorporationInventors: Shigeki Okatake, Yoshitaka Moriyasu, Masanori Masuda, Takenobu Nakamura
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Patent number: 11919995Abstract: An epoxy resin, comprising an epoxy compound having two or more mesogenic structures, and having a loss tangent of 1 or more at 35° C. before curing.Type: GrantFiled: February 18, 2019Date of Patent: March 5, 2024Assignee: RESONAC CORPORATIONInventors: Naoki Maruyama, Tomoko Higashiuchi, Kazumasa Fukuda, Hideyuki Katagi, Yuki Nakamura, Yoshitaka Takezawa
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Publication number: 20240074141Abstract: Methods and devices for a lateral three-dimensional memory device, are described herein. One method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a CMOS structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: Yoshitaka Nakamura, Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, David K. Hwang
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Patent number: 11848360Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.Type: GrantFiled: June 17, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Yoshitaka Nakamura, Devesh Dadhich Shreeram, Yi Fang Lee, Scott E. Sills, Jerome A. Imonigie, Kaustubh Shrimali
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Publication number: 20230400261Abstract: A Ni—Ti-based alloy contains a Ni atom, a Ti atom, and a Si atom. The Ni—Ti-based alloy has a heat-absorbing/generating property.Type: ApplicationFiled: November 8, 2021Publication date: December 14, 2023Inventors: Yoshitaka NAKAMURA, Kotaro ONO, Tatsuya NAKAMURA, Kentaro SHII
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Publication number: 20230397391Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.Type: ApplicationFiled: August 15, 2022Publication date: December 7, 2023Inventors: Si-Woo Lee, Scott E. Sills, David K. Hwang, Yoshitaka Nakamura, Yuanzhi Ma, Glen H. Walters
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Publication number: 20230397390Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.Type: ApplicationFiled: August 15, 2022Publication date: December 7, 2023Inventors: David K. Hwang, John F. Kaeding, Matthew S. Thorum, Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, Yoshitaka Nakamura, Glen H. Walters
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Patent number: 11703647Abstract: An optical fiber securing structure includes: an optical fiber including a coating, and a coating-removed section in which a partial section of the coating is removed from the optical fiber; a reinforcement member including main surfaces and a groove formed from one of the main surfaces toward an inside of the reinforcement member, where the groove has a pair of side walls and a bottom wall; and a resin member that secures the coating-removed section to the pair of side walls and the bottom wall. A bottom part of the groove that includes the bottom wall has a widthwise cross-sectional shape where the bottom wall constitutes a trapezoidal shape such that a distance between the pair of side walls becomes greater in a direction away from the bottom wall.Type: GrantFiled: September 14, 2020Date of Patent: July 18, 2023Assignee: Fujikura Ltd.Inventors: Ryokichi Matsumoto, Yoshitaka Nakamura, Naoyuki Sugiyama, Hiroto Nakazato, Yasushi Oikawa, Akari Takahashi
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Publication number: 20230010884Abstract: A heat transfer device includes a first member and a first and second heat transfer element. In the first heat transfer element, a first contact area that is a contact area between the first heat transfer element and the first member varies. In the second heat transfer element, a second contact area that is a contact area between the second heat transfer element and the first member varies. The first contact area is greater when magnitude of a first external force applied to the first member is smaller than a first threshold than when the magnitude of the first external force is equal to or greater than the first threshold. The second contact area is smaller when the magnitude of the first external force is smaller than the first threshold than when the magnitude of the first external force is equal to or greater than the first threshold.Type: ApplicationFiled: October 29, 2020Publication date: January 12, 2023Inventors: Kentaro SHII, Yoshitaka NAKAMURA, Tatsuya NAKAMURA, Yusuke OGIHARA
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Publication number: 20220406899Abstract: Some embodiments include an integrated assembly containing a first structure which includes one or more transition metals, and containing a second structure over the first structure. The second structure has a first region directly against the first structure and has a second region spaced from the first structure by a gap region. The second structure includes semiconductor material having at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Groups 15 and 16 of the periodic table. An ionic compound is within the gap region. Some embodiments include a method of forming an integrated assembly.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: Micron Technology, Inc.Inventors: Yoshitaka Nakamura, Devesh Dadhich Shreeram, Yi Fang Lee, Scott E. Sills, Jerome A. Imonigie, Kaustubh Shrimali
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Patent number: 11488963Abstract: A method including forming a first member having a first portion including a plurality of storage capacitors therein and a second portion surrounding the first portion; forming a second member of a concave shape having a third portion, which corresponds to a lower top surface of the concave shape, including a plurality of access transistors provided correspondingly to the plurality of storage capacitors therein and a fourth portion, which corresponds to an upper top surface of the concave shape, surrounding the third portion; stacking the first member on the second member to physically connect the second and fourth portions and have a gap between the first and third portions; cutting the first member to physically separate the first portion from the second portion; and joining the separated first portion and the third portion with filling the gap therebetween.Type: GrantFiled: August 18, 2020Date of Patent: November 1, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Mitsunari Sukekawa, Yoshitaka Nakamura
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Publication number: 20220327800Abstract: A classification unit classifies messages included in a text log depending on types, and gives an ID set for each type to each of the classified messages. A creation unit creates, based on dates of occurrence attached to the messages, a matrix indicating an appearance distribution of the messages in the text log for each predetermined duration for each ID. A pattern extraction unit extracts a plurality of patterns, which are combinations of the IDs, from the matrix created by the creation unit. A removal unit removes a part or whole of the patterns from the matrix. A determination unit calculates a degree of importance for each element included in each of the patterns, and determines whether the degree of importance is equal to or higher than a predetermined threshold. A sequence extraction unit extracts a sequence.Type: ApplicationFiled: June 22, 2022Publication date: October 13, 2022Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Shotaro TORA, Yoshitaka NAKAMURA, Machiko TOYODA
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Publication number: 20220269018Abstract: An optical fiber securing structure includes: an optical fiber including a coating, and a coating-removed section in which a partial section of the coating is removed from the optical fiber; a reinforcement member including main surfaces and a groove formed from one of the main surfaces toward an inside of the reinforcement member, where the groove has a pair of side walls and a bottom wall; and a resin member that secures the coating-removed section to the pair of side walls and the bottom wall. A bottom part of the groove that includes the bottom wall has a widthwise cross-sectional shape where the bottom wall constitutes a trapezoidal shape such that a distance between the pair of side walls becomes greater in a direction away from the bottom wall.Type: ApplicationFiled: September 14, 2020Publication date: August 25, 2022Applicant: FUJIKURA LTD.Inventors: Ryokichi Matsumoto, Yoshitaka Nakamura, Naoyuki Sugiyama, Hiroto Nakazato, Yasushi Oikawa, Akari Takahashi
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Patent number: 11422043Abstract: A pressure sensor 1 according to the first aspect of the invention includes: a substrate 50; and a functional element 40 which is laid on the substrate 50 and is composed of functional titanium oxide including crystal grains of at least one of ?-phase trititanium pentoxide (?-Ti3O5) and ?-phase trititanium pentoxide (?-Ti3O5) and having the property that at least a portion of crystal grains of at least one of ?-phase trititanium pentoxide (?-Ti3O5) and ?-phase trititanium pentoxide (?-Ti3O5) change into crystal grains of titanium dioxide (TiO2) when the functional titanium oxide is heated to 350° C. or higher. The substrate 50 includes a substrate thin-film section 51 having a thin film form in which the thickness in the stacking direction of the substrate 50 and the functional element 40 is smaller than that in the other directions.Type: GrantFiled: October 18, 2017Date of Patent: August 23, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshitaka Nakamura, Tsutomu Furuta, Hiroyoshi Yoden, Mitsuo Yaguchi, Takeshi Ueda
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Patent number: 11398083Abstract: A classification unit classifies messages included in a text log depending on types, and gives an ID set for each type to each of the classified messages. A creation unit creates, based on dates of occurrence attached to the messages, a matrix indicating an appearance distribution of the messages in the text log for each predetermined duration for each ID. A pattern extraction unit extracts a plurality of patterns, which are combinations of the IDs, from the matrix created by the creation unit. A removal unit removes a part or whole of the patterns from the matrix. A determination unit calculates a degree of importance for each element included in each of the patterns, and determines whether the degree of importance is equal to or higher than a predetermined threshold. A sequence extraction unit extracts a sequence.Type: GrantFiled: March 30, 2018Date of Patent: July 26, 2022Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Shotaro Tora, Yoshitaka Nakamura, Machiko Toyoda
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Patent number: 11393688Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.Type: GrantFiled: August 4, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Jerome A. Imonigie, Guangjun Yang, Anish A. Khandekar, Yoshitaka Nakamura, Yi Fang Lee
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Patent number: 11350879Abstract: A wearable device attached to a subject includes an accelerometer that measures acceleration information, and a biological sensor that measures biological signal information of the subject. From the measured acceleration information and biological signal information, first feature data corresponding to a first predetermined period and second feature data corresponding to a second predetermined period are extracted. By machine learning based on the first feature data, a dynamic/static activity identification model, a dynamic-activity identification model, and a static-activity identification model, for the subject, are generated. By combination of results of determination based on each of the identification models, a posture and an activity of the subject are identified, and correspondence information, which associates the identified posture and activity with the biological signal information of the subject, is generated.Type: GrantFiled: February 16, 2016Date of Patent: June 7, 2022Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Keitaro Horikawa, Yoshitaka Nakamura, Masato Sawada, Akihiro Yamanaka, Shingo Tsukada, Toshiya Yamada