Patents by Inventor Yoshitaka Nishihara

Yoshitaka Nishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153313
    Abstract: A training device including a motion data acquisition unit that acquires first motion data related to a target motion, a first generation unit that generates pseudo first motion data by using a first generation model, a determination unit that calculates a determination loss indicating a degree of deviation between the first motion data and the pseudo first motion data using a determination model, a relevance calculation unit that reconfigures the target motion by a combination of basis motions and calculate a degree of relevance between the target motion and the basis motions, a regularization loss calculation unit that calculates a regularization loss indicating a degree of deviation between motion data related to the basis motions and the pseudo first motion data, and an adversarial training processing unit that adversarially trains the first generation model and the determination model using the determination loss and the regularization loss.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 9, 2024
    Applicant: NEC Corporation
    Inventors: Kenichiro Fukushi, Yoshitaka Nozaki, Kosuke Nishihara, Kentaro Nakahara
  • Publication number: 20240144500
    Abstract: A data conversion device including a feature amount calculation unit that normalizes posture data estimated in each frame constituting moving image data including a synchronization target motion into an angular representation, and calculates a feature amount in an embedded space by inputting the posture data normalized into the angular representation to an encoder, a distance calculation unit that calculates a distance between a feature amount calculated in each frame constituting reference moving image data and a feature amount calculated in each frame constituting synchronization target moving image data, a synchronization processing unit that calculates an optimal path for each frame based on the calculated distance and synchronizes the synchronization target moving image data with the reference moving image data by aligning timings of frames connected by the optimal path, and an output unit that outputs the synchronization target moving image data synchronized with the reference moving image data.
    Type: Application
    Filed: October 16, 2023
    Publication date: May 2, 2024
    Applicant: NEC Corporation
    Inventors: Yoshitaka NOZAKI, Kenichiro Fukushi, Kosuke Nishihara, Kentaro Nakahara
  • Publication number: 20240125878
    Abstract: In separating water and fat with applying the Dixon method, peak intensities of fat with multiple peaks are individually calculated with a high degree of accuracy while reducing the number of variables to be estimated. Multiple images made up of signals acquired at different echo times (TEs) are used to solve a predetermined signal equation (signal model) expressing the relation between the pixel values (signal values) of the images and imaging parameters such as signal intensities of components and TE, thereby performing separation of signals for each component. For separating the signals, at least one of the variables (other than the signal intensity) included in the signal equation is subjected to a process (first estimation process) for refining a value roughly obtained, and then using thus refined value of the variable to estimate (second estimation process) other variables (including the signal intensity), the signals are separated.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 18, 2024
    Inventors: Takashi Nishihara, Toru Shirai, Yoshitaka Bito, Masahiro Takizawa
  • Publication number: 20240003053
    Abstract: In a SiC substrate of the present invention, in a case where the SiC substrate is supported on an inner periphery by an inner peripheral support surface positioned to overlap a circumference having a radius of 17.5 mm from a center, in a case where a plane connecting first points of an upper surface overlapping the inner peripheral support surface when seen in a thickness direction is defined as a first reference plane, and an upper side of the first reference plane is defined as a positive side, a bow is less than 40 ?m.
    Type: Application
    Filed: May 5, 2023
    Publication date: January 4, 2024
    Applicant: Resonac Corporation
    Inventors: Yoshitaka NISHIHARA, Hiromasa Suo
  • Publication number: 20230122232
    Abstract: A SiC ingot includes a seed crystal and a single crystal grown on the seed crystal, wherein the single crystal has therein a micropipe passing through the single crystal in a growth direction, and when photoluminescence observation is performed on a plurality of wafers cut out from the single crystal in a direction intersecting the growth direction, an S/N ratio of the micropipe in a first wafer cut out of the plurality of wafers, which is closest to the seed crystal, is higher than an S/N ratio of the micropipe in a second wafer cut out from a position further away from the seed crystal than the first wafer.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 20, 2023
    Applicant: SHOWA DENKO K.K.
    Inventor: Yoshitaka NISHIHARA
  • Publication number: 20230055999
    Abstract: A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a SiC single crystal substrate, the method including identifying a total number of large-pit defects caused by micropipes in the SiC single crystal substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, using microscopic and photoluminescence images. Also disclosed is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method including identifying locations of the large-pit defects caused by micropipes in the SiC single crystal substrate and the large-pit defects caused by substrate carbon inclusions in the SiC epitaxial layer, using microscopic and photoluminescence images.
    Type: Application
    Filed: November 4, 2022
    Publication date: February 23, 2023
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Keisuke Fukada
  • Publication number: 20220223482
    Abstract: A SiC epitaxial wafer including a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, and the number or positions of basal plane dislocations included in the high-concentration epitaxial layer have been identified
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 11315839
    Abstract: An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, irradiating a surface of the high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more with excitation light, and observing a surface irradiated with the excitation light via a band-pass filter having a wavelength band of 430 nm or less.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: April 26, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 11249027
    Abstract: A SiC epitaxial wafer, including: a SiC substrate; and an epitaxial layer stacked on a first surface of the SiC substrate, wherein an area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is identified, and the area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is equal to or less than ¼ of the first surface area of the SiC substrate.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 15, 2022
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 10985079
    Abstract: The invention provides a method of manufacturing a SiC epitaxial wafer in which stacking faults are less likely to occur when a current is passed in a forward direction. The method of manufacturing the SiC epitaxial wafer includes a measurement step for measuring a basal plane dislocation density, a layer structure determining process for determining the layer structure of the epitaxial layer, and an epitaxial growth step for growing the epitaxial layers. And in the layer structure determination step, in the case of (i) when the basal plane dislocation density is lower than a predetermined value, the epitaxial layer includes a conversion layer and a drift layer from the SiC substrate side; and in the case of (ii) when the density is equal to or higher than the predetermined value, the epitaxial layer includes a conversion layer, a recombination layer, and a drift layer from the SiC substrate side.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 20, 2021
    Assignee: SHOWA DENKO K.K.
    Inventor: Yoshitaka Nishihara
  • Patent number: 10985042
    Abstract: A SiC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SiC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 20, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Publication number: 20200388492
    Abstract: A method for manufacturing a SiC epitaxial wafer is provided. The method includes an observation step of observing a principal surface of a SiC substrate and identifying the presence or absence of a scratch having a depth of a predetermined value or more, a protrusion having a height of a predetermined value or more, or a foreign object having a height of a predetermined value or more, a polishing step of polishing the principal surface of the SiC substrate when it is identified that there is a scratch, the protrusion, or a foreign object and a layer forming step of forming a SiC epitaxial layer on the principal surface of the SiC substrate.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 10, 2020
    Applicant: SHOWA DENKO K. K.
    Inventor: Yoshitaka NISHIHARA
  • Publication number: 20200284732
    Abstract: A SiC epitaxial wafer, including: a SiC substrate; and an epitaxial layer stacked on a first surface of the SiC substrate, wherein an area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is identified, and the area occupied by bar-shaped stacking faults on the first surface of the SiC substrate is equal to or less than ¼ of the first surface area of the SiC substrate.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Publication number: 20200251561
    Abstract: A SiC epitaxial wafer includes a SiC epitaxial layer formed on a SiC single crystal substrate, in which a total density of large-pit defects caused by micropipes in the substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, is 1 defect/cm2 or less.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 6, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Keisuke FUKADA
  • Patent number: 10697898
    Abstract: In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 30, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Publication number: 20200152528
    Abstract: The invention provides a method of manufacturing a SiC epitaxial wafer in which stacking faults are less likely to occur when a current is passed in a forward direction. The method of manufacturing the SiC epitaxial wafer includes a measurement step for measuring a basal plane dislocation density, a layer structure determining process for determining the layer structure of the epitaxial layer, and an epitaxial growth step for growing the epitaxial layers. And in the layer structure determination step, in the case of (i) when the basal plane dislocation density is lower than a predetermined value, the epitaxial layer includes a conversion layer and a drift layer from the SiC substrate side; and in the case of (ii) when the density is equal to or higher than the predetermined value, the epitaxial layer includes a conversion layer, a recombination layer, and a drift layer from the SiC substrate side.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 14, 2020
    Applicant: SHOWA DENKO K.K.
    Inventor: Yoshitaka NISHIHARA
  • Publication number: 20200116649
    Abstract: In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 16, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Publication number: 20200118854
    Abstract: A SIC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SIC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 16, 2020
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Publication number: 20190172758
    Abstract: An evaluation method of a SiC epitaxial wafer includes: a first observation step of preparing a SiC epitaxial wafer having a high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more, irradiating a surface of the high-concentration epitaxial layer having an impurity concentration of 1×1018 cm?3 or more with excitation light, and observing a surface irradiated with the excitation light via a band-pass filter having a wavelength band of 430 nm or less.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 6, 2019
    Applicant: SHOWA DENKO K.K.
    Inventors: Yoshitaka NISHIHARA, Koji KAMEI
  • Patent number: 6941789
    Abstract: After molding is started, a large reaction force is obtained by compressing the air within a lower chamber by a piston while maintained in a sealing state. At an intermediate time of the molding, a small reaction force is obtained by communicating the upper and lower chambers with each other by a switching portion of a spool. At a final time of the molding, a large reaction force is again obtained by interrupting a flow path between the upper and lower chambers. The die cushion ability can be mechanically switched in association with the stroke of the piston, the die cushion device can be set such that no time lag is easily caused at a switching time, and the die cushion ability can be instantly switched.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 13, 2005
    Assignee: Komatsu Ltd.
    Inventor: Yoshitaka Nishihara