Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: A semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a semiconductor material layer, a memory opening and a support opening extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a semiconductor material portion in contact with the semiconductor material layer, and a support pillar structure located in the support opening. The support pillar structure lacks a semiconductor material portion which is in contact with the semiconductor material layer.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each alternating stack within the plurality of alternating stacks is laterally spaced apart from one another by a network of interconnected trenches that extend through each level of the insulating layers and the electrically conductive layers. Groups of memory stack structures extend through a respective one of the alternating stacks. The network of interconnected trenches includes first lengthwise trenches laterally extending along a first horizontal direction by a first lateral trench extension distance, second lengthwise trenches laterally extending along the first horizontal direction and interlaced with the first lengthwise trenches to provide a laterally alternating sequence, and widthwise trenches connecting an end of a respective one of the second lengthwise trenches to a portion of a sidewall of a first lengthwise trench.

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory openings are formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer. A memory film is formally formed by a conformal deposition process, and a source contact layer is formed in the source cavity. Vertical semiconductor channels and drain regions are formed in remaining volumes of the memory openings on sidewalls of the source contact layer. A backside contact via structure is formed through the alternating stack and directly on a sidewall of the source contact layer.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate. Each alternating stack within the plurality of alternating stacks is laterally spaced apart from one another by a network of interconnected trenches that extend through each level of the insulating layers and the electrically conductive layers. Groups of memory stack structures extend through a respective one of the alternating stacks. The network of interconnected trenches includes first lengthwise trenches laterally extending along a first horizontal direction by a first lateral trench extension distance, second lengthwise trenches laterally extending along the first horizontal direction and interlaced with the first lengthwise trenches to provide a laterally alternating sequence, and widthwise trenches connecting an end of a respective one of the second lengthwise trenches to a portion of a sidewall of a first lengthwise trench.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.

Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.

Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers with patterned stepped surfaces and an overlying retro-stepped dielectric material portion. The backside openings may be formed in rows with shape modifications in staircase regions to provide more lateral elongation in areas with lesser layers of the alternating stack. Non-circular horizontal cross-sectional shapes for the backside openings in the staircase regions allow formation of the backside opening with less shape distortion. Memory opening fill structures are formed in the memory openings, and the sacrificial material layers are replaced with electrically conductive layers using the backside openings as conduits for an etchant and for a deposition precursor material. The electrically conductive layers are isotropically recessed around each backside opening to form width-modulated cavities, which is filled with width-modulated insulating wall structures.

Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.