Patents by Inventor Yoshitaka Otsu

Yoshitaka Otsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190348435
    Abstract: Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers with patterned stepped surfaces and an overlying retro-stepped dielectric material portion. The backside openings may be formed in rows with shape modifications in staircase regions to provide more lateral elongation in areas with lesser layers of the alternating stack. Non-circular horizontal cross-sectional shapes for the backside openings in the staircase regions allow formation of the backside opening with less shape distortion. Memory opening fill structures are formed in the memory openings, and the sacrificial material layers are replaced with electrically conductive layers using the backside openings as conduits for an etchant and for a deposition precursor material. The electrically conductive layers are isotropically recessed around each backside opening to form width-modulated cavities, which is filled with width-modulated insulating wall structures.
    Type: Application
    Filed: March 25, 2019
    Publication date: November 14, 2019
    Inventors: Koichiro Nagata, Junpei Kanazawa, Yoshitaka Otsu, Takaaki Iwai, Shuji Minagawa, Hisakazu Otoi
  • Patent number: 10304830
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 28, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Morii, Yoshitaka Otsu
  • Publication number: 20180294265
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Application
    Filed: June 8, 2018
    Publication date: October 11, 2018
    Inventors: Katsumi MORII, Yoshitaka OTSU
  • Patent number: 10020305
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 10, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Morii, Yoshitaka Otsu
  • Publication number: 20170162572
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 8, 2017
    Inventors: Katsumi MORII, Yoshitaka OTSU
  • Patent number: 9614076
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Grant
    Filed: August 10, 2014
    Date of Patent: April 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi Morii, Yoshitaka Otsu
  • Publication number: 20150041960
    Abstract: There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment.
    Type: Application
    Filed: August 10, 2014
    Publication date: February 12, 2015
    Inventors: Katsumi MORII, Yoshitaka OTSU
  • Patent number: 8692352
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Patent number: 8569839
    Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Morii, Yoshitaka Otsu, Kazuma Onishi, Tetsuya Nitta, Tatsuya Shiromoto, Shigeo Tokumitsu
  • Patent number: 8357989
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: January 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Publication number: 20110175205
    Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 21, 2011
    Inventors: Katsumi MORII, Yoshitaka OTSU, Kazuma ONISHI, Tetsuya NITTA, Tatsuya SHIROMOTO, Shigeo TOKUMITSU
  • Publication number: 20110062547
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 17, 2011
    Inventors: Kazuma ONISHI, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii
  • Publication number: 20070166969
    Abstract: The invention provides a semiconductor device capable of protecting a low-concentration implantation region from contamination, and a method for manufacturing the same. A photoresist is formed on a TEOS film which is formed all over a substrate, and removed by photo engraving so as to be partially left. This photo resist is of a positive or negative type opposite to a type of a photoresist used for formation of a p-offset region and a diffusion region. Then, the TEOS film is etched back except for a portion just under the photoresist. Thereby, a contamination protective film is formed just under the photoresist, and a side wall is formed on a side face of a gate electrode.
    Type: Application
    Filed: January 16, 2007
    Publication date: July 19, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Shinichiro YANAGI, Yoshitaka Otsu, Takayuki Igarashi, Yasuki Yoshihisa
  • Patent number: RE46773
    Abstract: A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 3, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuma Onishi, Yoshitaka Otsu, Hiroshi Kimura, Tetsuya Nitta, Shinichiro Yanagi, Katsumi Morii