Patents by Inventor Yoshito Nakazawa
Yoshito Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876127Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.Type: GrantFiled: August 18, 2021Date of Patent: January 16, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tomohiro Imai, Yoshito Nakazawa, Katsumi Eikyu
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Patent number: 11830939Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.Type: GrantFiled: August 18, 2021Date of Patent: November 28, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tomohiro Imai, Yoshito Nakazawa, Katsumi Eikyu
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Publication number: 20220102538Abstract: A semiconductor device according to one embodiment includes an IGBT having a p-type collector layer and an n-type field stop layer on a back surface of a silicon substrate. The n-type field stop layer is selectively provided on an upper side of the p-type collector layer such that a first end portion of the n-type field stop layer is separated from a first side surface of the silicon substrate by a predetermined distance, and an n-type drift layer is provided between the first side surface of the silicon substrate and the first end portion of the n-type field stop layer. An impurity concentration of the n-type drift layer is lower than an impurity concentration of the n-type field stop layer.Type: ApplicationFiled: August 18, 2021Publication date: March 31, 2022Inventors: Yoshito NAKAZAWA, Tomohiro IMAI
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Publication number: 20220069111Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.Type: ApplicationFiled: August 18, 2021Publication date: March 3, 2022Inventors: Tomohiro IMAI, Yoshito NAKAZAWA, Katsumi EIKYU
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Patent number: 11107912Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.Type: GrantFiled: February 11, 2019Date of Patent: August 31, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 10903354Abstract: A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a <010> direction, a second region extending in a <001> direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the <010> direction in the first region and a second opening extending in the <001> direction in the second region, and the first opening and the second opening are divided from each other in the third region.Type: GrantFiled: April 1, 2019Date of Patent: January 26, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yoshito Nakazawa
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Patent number: 10475882Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation <011>. Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation <011>, and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation <010> and the crystal orientation <011>.Type: GrantFiled: May 4, 2018Date of Patent: November 12, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shigeaki Saito, Yoshito Nakazawa, Hitoshi Matsuura, Yukio Takahashi
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Publication number: 20190326432Abstract: A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a <010> direction, a second region extending in a <001> direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the <010> direction in the first region and a second opening extending in the <001> direction in the second region, and the first opening and the second opening are divided from each other in the third region.Type: ApplicationFiled: April 1, 2019Publication date: October 24, 2019Inventor: Yoshito NAKAZAWA
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Publication number: 20190189798Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: Yoshito NAKAZAWA, Yuji YATSUDA
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Patent number: 10211332Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.Type: GrantFiled: December 1, 2017Date of Patent: February 19, 2019Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20180350910Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation <011>. Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation <011>, and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation <010> and the crystal orientation <011>.Type: ApplicationFiled: May 4, 2018Publication date: December 6, 2018Applicant: Renesas Electronics CorporationInventors: Shigeaki SAITO, Yoshito NAKAZAWA, Hitoshi MATSUURA, Yukio TAKAHASHI
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Publication number: 20180090610Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.Type: ApplicationFiled: December 1, 2017Publication date: March 29, 2018Inventors: Yoshito NAKAZAWA, Yuji YATSUDA
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Patent number: 9837528Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.Type: GrantFiled: October 25, 2016Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 9825167Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.Type: GrantFiled: August 15, 2016Date of Patent: November 21, 2017Assignee: Renesas Electronics CorporationInventors: Hitoshi Matsuura, Yoshito Nakazawa
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Patent number: 9786736Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.Type: GrantFiled: March 4, 2016Date of Patent: October 10, 2017Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa
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Patent number: 9660070Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.Type: GrantFiled: January 12, 2016Date of Patent: May 23, 2017Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa, Satoshi Eguchi
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Publication number: 20170040445Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.Type: ApplicationFiled: October 25, 2016Publication date: February 9, 2017Inventors: Yoshito NAKAZAWA, Yuji YATSUDA
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Patent number: 9520318Abstract: A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.Type: GrantFiled: January 14, 2016Date of Patent: December 13, 2016Assignee: Renesas Electronics CorporationInventors: Satoshi Eguchi, Yoshito Nakazawa
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Publication number: 20160351703Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.Type: ApplicationFiled: August 15, 2016Publication date: December 1, 2016Inventors: Hitoshi MATSUURA, Yoshito Nakazawa
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Patent number: 9478530Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.Type: GrantFiled: January 20, 2016Date of Patent: October 25, 2016Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda