Patents by Inventor Yoshito Nakazawa
Yoshito Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9013006Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.Type: GrantFiled: December 9, 2013Date of Patent: April 21, 2015Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20150097237Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.Type: ApplicationFiled: December 14, 2014Publication date: April 9, 2015Inventors: Tomohiro TAMAKI, Yoshito NAKAZAWA
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Patent number: 8987819Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.Type: GrantFiled: June 27, 2014Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa
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Patent number: 8981469Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.Type: GrantFiled: September 25, 2013Date of Patent: March 17, 2015Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa
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Publication number: 20150054069Abstract: A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes.Type: ApplicationFiled: October 30, 2014Publication date: February 26, 2015Inventors: Nobuyuki SHIRAI, Nobuyoshi MATSUURA, Yoshito NAKAZAWA
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Patent number: 8937350Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: January 31, 2014Date of Patent: January 20, 2015Assignee: Renesas Electronics CorporationInventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Publication number: 20150011081Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: September 22, 2014Publication date: January 8, 2015Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
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Patent number: 8928071Abstract: A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.Type: GrantFiled: March 16, 2013Date of Patent: January 6, 2015Assignee: Renesas Electronics CorporationInventors: Nobuyuki Shirai, Nobuyoshi Matsuura, Yoshito Nakazawa
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Publication number: 20140312418Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.Type: ApplicationFiled: June 27, 2014Publication date: October 23, 2014Inventors: Tomohiro TAMAKI, Yoshito NAKAZAWA
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Publication number: 20140299961Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Tomohiro TAMAKI, Yoshito NAKAZAWA, Satoshi EGUCHI
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Publication number: 20140235020Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke ARAI, Yoshito NAKAZAWA, Ikuo HARA, Tsuyoshi KACHI, Yoshinori HOSHINO, Tsuyoshi TABATA
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Publication number: 20140225189Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: ApplicationFiled: April 23, 2014Publication date: August 14, 2014Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
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Patent number: 8796787Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.Type: GrantFiled: September 27, 2013Date of Patent: August 5, 2014Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa
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Patent number: 8786046Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.Type: GrantFiled: June 5, 2013Date of Patent: July 22, 2014Assignee: Renesas Electronics CorporationInventors: Tomohiro Tamaki, Yoshito Nakazawa, Satoshi Eguchi
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Publication number: 20140193968Abstract: A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.Type: ApplicationFiled: December 9, 2013Publication date: July 10, 2014Applicant: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20140191309Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.Type: ApplicationFiled: December 17, 2013Publication date: July 10, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Satoshi EGUCHI, Yoshito NAKAZAWA, Tomohiro TAMAKI
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Patent number: 8748266Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.Type: GrantFiled: November 8, 2011Date of Patent: June 10, 2014Assignees: Renesas Electronics Corporation, Hitachi Ulsi Systems Co., Ltd.Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
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Patent number: 8741699Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.Type: GrantFiled: May 24, 2012Date of Patent: June 3, 2014Assignee: Renesas Electronics CorporationInventors: Daisuke Arai, Yoshito Nakazawa, Ikuo Hara, Tsuyoshi Kachi, Yoshinori Hoshino, Tsuyoshi Tabata
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Publication number: 20140145260Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: ApplicationFiled: January 31, 2014Publication date: May 29, 2014Applicant: Renesas Electronics CorporationInventors: Hitoshi MATSUURA, Yoshito NAKAZAWA, Tsuyoshi KACHI, Yuji YATSUDA
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Patent number: 8659078Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: March 10, 2013Date of Patent: February 25, 2014Assignee: Renesas Electronics CorporationInventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda