Abstract: A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories.

Abstract: A method and system are provided for concentrating calls for a packet switching system in a hierarchical communication network. A plurality of terminals communicate with an associated plurality of packet concentrators that, in turn, communicate with switching equipment. The system and method comprise initiating a call at a call terminal to be communicated to the packet concentrator and identifying the call terminal by associating a line number communicating the terminal with the concentrator with a first logical channel number for communication from the packet concentrator to the switching equipment.

Abstract: A switching system for handling a plurality of cells, each cell including a header section and a data section, and for exchanging a communication message contained in the data section of the cell between a plurality of incoming highways and a plurality of outgoing highways according to the data contained in the header section of the cell. The switching system includes a unit for multiplexing the incoming highways in time division, a first memory having addressable storage locations for storing cells received from the multiplexing unit, a unit for demultiplexing and distributing data output from the first memory among a plurality of outgoing highways, a second memory for storing an empty address of an empty storage location of the first memory, a unit for controlling the write and read operations of the first memory in accordance with an empty address stored in the second memory used as write and read addresses, and a unit for detecting an error in at least one of the write address and read address.

Abstract: A switching system for switching communication information between "M" incoming highways and "N" outgoing highways by using fixed-length cells, each having a header section and a data section and according to information contained in the header section (where "M" and "N" are integers), comprising: a demultiplexing unit for demultiplexing each incoming highway into a plurality of first output links; a switch unit, having the first output links of the demultiplexing unit as first input links and a plurality of second output links, for switching communication information between the first input links and the second output links; and a multiplexing unit, having "N" groups of input links, each group being formed by grouping a specified number of second output links, for multiplexing the cells on the second output links of each group and outputting them through one of third output links to a corresponding outgoing highway.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunkline, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: In the ATM switching system, an ATM speech path is divided into a plurality of functional blocks. A routing function for distributing cells (packets) each of a fixed length to addresses outgoing lines and a logical multiplexing function are imparted to a switch, while other functions associated with a line typified by a phase synchronizing function and a flow control function are incorporated en bloc in ATM line terminating units and functions capable of being processed by hardware in common to the lines are assembled in a line common unit. The ATM line terminating unit physically terminates transmission lines and performs the processing relevant to header information of the cells each of a fixed length (ATM terminating processing) and includes a cell phase synchronizing circuit for matching the temporal positions of the cells among the lines and a flow control circuit for avoiding overload exceeding the load declared by subscriber terminal.

Abstract: A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions.

Abstract: A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.